- 13 Mar, 2014 3 commits
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Ezequiel Garcia authored
The Armada 38x SoC family has a NAND controller, compatible with the controller in Armada 370/375/XP SoCs. Add support for it in the devicetree file. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-5-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by:
Jason Cooper <jason@lakedaemon.net>
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Ezequiel Garcia authored
The Armada 38x SoC family has a clock provider called "Core Divider", derived from the fixed 2 GHz main PLL clock. This is similar to the one on A370, A375 and AXP. Signed-off-by:
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Ezequiel Garcia authored
Armada 38x SoCs have a 2 GHz fixed main PLL that is used to feed other clocks. This commit adds a DT representation of this clock through a fixed-clock compatible node. Signed-off-by:
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- 06 Mar, 2014 7 commits
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Sebastian Hesselbarth authored
Marvell Dove's pinctrl does require some PMU regs for muxing PMU functions to MPP pins. Recently, a discussion started about consolidating Power Management Unit (PMU) into a single DT node. As we don't want anymore DT ABI in the way, drop the corresponding reg property from pinctrl node now. The driver will derive the registers from existing reg properties. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Gregory CLEMENT authored
The Armada 385 RD board is the reference design board from Marvell for the Armada 385 SoC. This commit adds a Device Tree description for this board, which enables the following features: * Network interfaces * I2C bus * Serial port * SPI bus, with a SPI flash * PCIe interface Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Thomas Petazzoni authored
On Armada 385 DB, while the "rgmii" PHY connection mode works fine with the generic PHY driver, it fails to work when the Marvell PHY driver is enabled in the kernel configuration, due to a finer handling of the PHY configuration. This is due to the fact that the phy connection mode should instead be "rgmii-id", i.e with the TX/RX delay mechanisms enabled. This fixes the network operation on Armada 385 DB with CONFIG_MARVELL_PHY=y. Without this patch and this option enabled, one would only get messages such as: mvneta f1070000.ethernet eth1: bad rx status 0cc10000 (crc error), size=70 Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
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Thomas Petazzoni authored
Since the Armada XP Matrix board has 4 GB of RAM and not 2 GB, we update the Device Tree to take into account the correct amount of memory. As noted in the new comment, the last 256 MB of RAM are in fact not usable, due to the overlap with the MBus Window address range. Signed-off-by:
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Thomas Petazzoni authored
Marvell has now provided bootloaders that are Device Tree capable for the Armada XP GP board, and that also remap the internal register base address to 0xf1000000. In addition, the bootloader now sets the MBus Window base address to 0xf0000000, which allows to use much more RAM in the last GB of RAM before the 4 GB limit (the entire space from 0xC0000000 to 0xFFFFFFFF was not usable due to being used for I/O, not only the space from 0xF0000000 to 0xFFFFFFFF is used for I/O). Therefore this commit: * Updates the memory->reg Device Tree property with the fact that in the first bank of RAM, memory up to 0xf0000000 can be used. * Updates the soc->ranges Device Tree property with the fact that the internal registers are now mapped at 0xf1000000. Signed-off-by:
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Thomas Petazzoni authored
Marvell has now provided bootloaders that are Device Tree capable for the Armada XP DB board, and that also remap the internal register base address to 0xf1000000. In addition, the bootloader now sets the MBus Window base address to 0xf0000000, but on this board, this change doesn't make much difference since the board is by default equipped with 2 GB of RAM. Therefore this commit updates the soc->ranges Device Tree property with the fact that the internal registers are now mapped at 0xf1000000. Signed-off-by:
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Thomas Petazzoni authored
The latest Marvell bootloaders for various boards change the MBus Window base address from 0xC0000000 to 0xF0000000, in order to make more RAM in the first 4 GB actually usable by the kernel (RAM that is covered by the MBus window is "shadowed" and therefore not usable). However, our default PCIe memory and I/O apertures where sitting at 0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be outside of the MBus Window range on those platforms. To make things work, we have to ensure those apertures use addresses in the 0xF0000000 -> 0xFFFFFFFF range. Of course this change of the MBus Window base address from 0xC0000000 to 0xF0000000 also comes with a change of the internal register base address from 0xD0000000 to 0xF1000000. We have therefore designed the following memory map: * 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP GP and Armada XP DB. * 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers. * 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory. * 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O. * 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping There is one exception to this layout: the Armada XP OpenBlocks, which has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This does not conflict with the current change for the PCIe I/O and memory apertures, and continues to work because on Armada XP OpenBlocks, the bootloader is an old one, and continues to have internal registers mapped at 0xD0000000. Signed-off-by:
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- 04 Mar, 2014 10 commits
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Sebastian Hesselbarth authored
This adds a DT node for the system-controller found on Marvell Dove SoCs. Signed-off-by:
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Andrew Lunn authored
Describe the T5325 using device tree properties, where possible. The first version of this file was produced by Thomas Petazzoni. Signed-off-by:
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Andrew Lunn authored
When using platform_driver instantiation, the i2c bus was given bus number 0. The kirkwood-t5325 audio driver has this bus number hard coded for the address of the codec. However by default device tree i2c busses are dynamically allocated a bus number, starting from 1. Thus the kirkwood-t5325 cannot find its audio codec. By adding an alias in the DT file we can control the bus number and set it to 0. The codec can then be found. Signed-off-by:
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Andrew Lunn authored
The binding has existed for a while, so add the missing node so it can be used by devices. Signed-off-by:
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Jason Cooper authored
With kirkwood migrating into mach-mvebu, mvebu_v5_defconfig needs to select ARCH_MVEBU. Unfortunately, this means that when building a v5 kernel, we unnecessarily build dtbs for the armada v7 boards. To fix this, we instead select based on MACH_ARMADA_* on a per SoC basis. Reported-by:
Kevin Hilman <khilman@linaro.org> Acked-by:
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Jason Cooper authored
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Sebastian Hesselbarth authored
We share global config registers by syscon node, add it to dove.dtsi. Signed-off-by:
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Sebastian Hesselbarth authored
Dove pinctrl uses additional registers to control MPPs. This patch first increases existing pinctrl reg property by one register, and then adds two new ranges for MPP4 and PMU MPP registers. Signed-off-by:
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Andrew Lunn authored
Make use of the mvebu system controller, by placing a node into the dtsi file. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Tested-by:
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by:
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Andrew Lunn authored
Now that the Feroceon L2 cache has a DT binding, make use of it. Signed-off-by:
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- 22 Feb, 2014 7 commits
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Jason Cooper authored
mvebu dt fixes for v3.14 - mvebu: add missing 'eth3' alias for mv78260 - dove: revert PMU interrupt controller node, wait for driver to land.
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Thomas Petazzoni authored
Instead of hardcoding the values of the interrupt flags, use the macros provided by <include/dt-bindings/interrupt-controller/irq.h> and <include/dt-bindings/interrupt-controller/arm-gic.h> for the Armada 375 and Armada 38x Device Tree files. Signed-off-by:
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Thomas Petazzoni authored
Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts, use the definitions of <dt-bindings/interrupt-controller/arm-gic.h> to clarify the Device Tree code. Signed-off-by:
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Thomas Petazzoni authored
Some of the Armada 375/38x DTs that were recently submitted were still using the old-style /include/ instead of the new-style, C-preprocessor based #include. Since we are going to start including more headers, switching to the C-preprocessor based includes is important. Signed-off-by:
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Ben Peddell authored
Add device tree fragments and files to support many of the kirkwood based Synology NAS devices. This is a modification of Andrew Lunn's <andrew@lunn.ch> translation of the board setup file maintained by Ben Peddell <klightspeed@killerwolves.net> The Ricoh RS5C372 RTC was used in all 2009 units and some 2010 units. All other Synology Kirkwood-based DiskStations and RackStations use the Seiko S35390A RTC. Most of the 1-bay and 2-bay units use the GPIOs that are multiplexed with the built-in SATA interface activity/presence pins on mpp 20-23, while the 4-bay units use ge01 and a PCIe SATA controller, and put the software controlled HDD leds on mpp 36-43. Most of the 6281 units with HDD power controls use mpp 29 and 31, while most of the 6282 units with HDD power controls use mpp 30, 34, 44 and 45 and provide a model ID on mpp 28, 29, 46 and 47. Pre-2012 units and most 4-bay units didn't have a separate power control for HDD1. These power controls are presumably to limit startup current from the 12V brick power supply. Instead of using separate dtsi files in a synology directory, this patch uses a single dtsi file containing all of the modules for these boards, with all of the modules not common to all boards disabled. The board dts files then enable the appropriate modules for their boards. Signed-off-by:
Ben Peddell <klightspeed@killerwolves.net> Tested-by: Ben Peddell <klightspeed@killerwolves.net> (ds211j) Signed-off-by:
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Andrew Lunn authored
Add the Seiko Instruments Inc S35390a to the list of trivial i2c devices. Signed-off-by:
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Andrew Lunn authored
The following patches make use of vendor names: * ricoh (Ricoh Co. Ltd.); * qnap (QNAP Systems, Inc.); * sii (Seiko Instruments, Inc.); and * synology (Synology, Inc.) Add them to the vendor prefix list. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 18 Feb, 2014 1 commit
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Jason Cooper authored
The corresponding driver didn't make it into v3.14, so we need to remove the node. Dove systems fail to boot with the node present and no driver. This node will be re-added when the driver makes it to mainline. Reported-by:
Jean-Francois Moine <moinejf@free.fr> Tested-by:
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- 17 Feb, 2014 12 commits
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Thomas Petazzoni authored
The Armada 385 DB board is the development board from Marvell for the Armada 385 SoC. This commit adds a Device Tree description for this board, which enables the following features: * Network interfaces * I2C buses * SDIO * Serial port * SPI bus, with a SPI flash * PCIe interfaces Signed-off-by:
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Thomas Petazzoni authored
The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a Cortex-A9 cores (single core for 380, dual core for 385) and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPU * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * Pinctrl * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers * Network interfaces Signed-off-by:
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Thomas Petazzoni authored
The Armada 375 DB board is the development board from Marvell for the Armada 375 SoC. This commit adds a Device Tree description for this board, which enables the following features: * I2C buses * SDIO * Serial port * SPI bus, with a SPI flash. Note that the SPI bus is disabled by default, because it conflicts with the NAND, and can only work if the board boots out of SPI. Since most boards are shipped to boot out of NAND, we're default to having the SPI bus disabled. * PCIe interfaces Signed-off-by:
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Gregory CLEMENT authored
The Armada 375 SoC is a new SoC from Marvell, based on a dual core Cortex-A9 and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPUs * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * SDIO * Pinctrl * SATA * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers Signed-off-by:
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Ezequiel Garcia authored
Add the devicetree node to enable watchdog support available in Dove SoCs. Tested-by:
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Ezequiel Garcia authored
In order to support multiplatform builds the watchdog devicetree binding was modified and now the 'reg' property is specified to need two entries. This commit adds the second entry as-per the new specification. Tested-by:
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Ezequiel Garcia authored
Add the DT nodes to enable watchdog support available in Armada 370 and Armada XP SoCs. Tested-by:
Willy Tarreau <w@1wt.eu> Signed-off-by:
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Andrew Lunn authored
Perform a mechanical translation of rd88f6281-setup.c into DT. Since the hardware differs between the A0 and A1 stepping, two dts files are used, and a .dtsi file for the common parts. The A0 part does not have a "wan" port on the switch and uses PHY address 10 to address the switch. The A1 part does have the "wan" port and uses address 0. Signed-off-by:
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Andrew Lunn authored
Mechanically translate rd88f6192-nas-setup.c into DT equivelent. Signed-off-by:
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Thomas Petazzoni authored
In addition to the analog audio input and output, the Armada 370 DB also has S/PDIF input and output optical connectors. This commit improves the Device Tree description of the Armada 370 DB platform to enable the S/PDIF support. Signed-off-by:
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Thomas Petazzoni authored
This commit adds the necessary Device Tree informations to enable audio support on the Armada 370 DB platform. In details it: * Instantiates the CS42L51 audio codec on the I2C0 bus, and configures this bus with the appropriate pin-muxing configuration. * Enables the I2S audio controller, and configures it with the appropriate pin-muxing configuration. * Through hog pins, ensures that the other pins possibly used for I2S are muxed with another function than I2S. Signed-off-by:
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Thomas Petazzoni authored
This commit adds a pin-muxing configuration for the I2C0 bus of the Armada 370, which is used on the Armada 370 DB platform to interface with the CS42L51 audio codec. Signed-off-by:
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