Commits · 94d52a355f19286c7091c11ca23e9a602fe4d25e · Kirill Smelkov / linux

16 Nov, 2020 6 commits

drm/amdgpu: update golden setting for sienna_cichlid · 94d52a35

Likun Gao authored Nov 16, 2020

Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

94d52a35

drm/amd/pm: update driver if file for sienna cichlid · 34d903d1

Likun Gao authored Nov 16, 2020

Update driver if file for sienna cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

34d903d1

drm/amd/pm: enable the fine grain tuning function for vangogh · 93a80241

Xiaojian Du authored Nov 12, 2020

This patch is to enale the fine grain tuning function for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

93a80241

drm/amd/pm: add the fine grain tuning function for vangogh · c98ee897

Xiaojian Du authored Nov 12, 2020

This patch is to add the fine grain tuning function for vangogh.
This function uses the pp_od_clk_voltage sysfs file to configure the min
and max value of gfx clock frequency or restore the default value.

Command guide:
echo "s level value" > pp_od_clk_voltage
        "s" - set the sclk frequency
        "level" - 0 or 1, "0" represents the min value,  "1" represents
        the max value
        "value" - the target value of sclk frequency, it should be
        limited in the safe range
echo "r" > pp_od_clk_voltage
	"r" - reset the sclk frequency, restore the default value
        instantly
echo "c" > pp_od_clk_voltage
        "c" - commit the min and max value of sclk frequency to the system
        only after the commit command, the setting target values by "s" command
        will take effect.
Example:
1)check the default sclk frequency
	$ cat pp_od_clk_voltage
	OD_SCLK:
	0:        200Mhz
	1:       1400Mhz
	OD_RANGE:
	SCLK:     200MHz       1400MHz
2)use "s" -- set command to configure the min or max sclk frequency
	$ echo "s 0 600" > pp_od_clk_voltage
	$ echo "s 1 1000" > pp_od_clk_voltage
	$ echo "c" > pp_od_clk_voltage
        $ cat pp_od_clk_voltage
	OD_SCLK:
	0:        600Mhz
	1:       1000Mhz
	OD_RANGE:
	SCLK:     200MHz       1400MHz
3)use "r" -- reset command to restore the min and max sclk frequency
	$ echo "r" > pp_od_clk_voltage
        $ cat pp_od_clk_voltage
	OD_SCLK:
	0:        200Mhz
	1:       1400Mhz
	OD_RANGE:
	SCLK:     200MHz       1400MHz
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

c98ee897

drm/amd/display: Update dmub code · 5fe6b98a

Bhawanpreet Lakha authored Nov 13, 2020

There is a delta in the dmub code
- add boot options
- add boot status
- remove unused auto_load_is_done func pointer
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5fe6b98a

drm/amdgpu: fix usable gart size calculation · b3fcde18

Nirmoy Das authored Nov 12, 2020

amdgpu_do_test_moves() is failing because of wrong
usable gart size calculation and throwing:

[drm:amdgpu_do_test_moves [amdgpu]] *ERROR* 0000000020bdc9f3 bind failed
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b3fcde18

13 Nov, 2020 34 commits

drm/amd/display: Extract 3rd plane from metadata · 1331e630

Bas Nieuwenhuizen authored Nov 11, 2020

Now that we actually expose the right number of planes we get
problems with modifier aware libva if we use an unsupported modifier.

So this ensures that we as much as possible use a modifier that
radeonsi can actually render to without going to extreme difficulty
to synchronize an extra DCC metadata plane with implicit sync.

Looking into the opaque metadata isn't ideal but this converts to
something mainly for the purpose of the userspace driver and falls
back properly if it isn't what we expect.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1331e630

drm/amd/display: Set new format info for converted metadata. · 816853f9

Bas Nieuwenhuizen authored Nov 11, 2020

If we use DCC modifiers this can increase the number of planes from
the initial 1 plane with metadata, so that we get a valid modifier
from getfb2.

Since the code didn't update the format_info getfb2 would only ever
return 1 plane with a modifier for which userspace expects > 1.

This moves the format lookup to amdgpu_display.c so we do not have
issues when DC is not compiled.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

816853f9

drm/amd/display: Store gem objects for planes 1-3 · 3505b2ff

Bas Nieuwenhuizen authored Nov 11, 2020

Also do the proper validation which was missed.

Besides the missing validation, not storing the objects in the
framebuffer led to wrong results in the getfb2 ioctl.

Note that this should really have been done for multi-plane
formats like NV12 already before modifiers landed.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3505b2ff

drm/fourcc: add table describing AMD modifiers bit layout · 544645f2

Simon Ser authored Nov 13, 2020

The table describes how each bit in the u64 value is used. Explicitly
state which values a field can take if we have defines for them. Also
add a note when a field isn't always populated.

Forcing people to update the table when changing the bit layout should
make it more obvious when there's a mistake, I hope.

If we get to the point where the bit layout gets more complicated, it
might be worth it to split the table into multiple tables (e.g. one for
GFX8, one for GFX9+, and so on).
Signed-off-by: Simon Ser <contact@emersion.fr>
Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

544645f2

drm/fourcc: Fix modifier field mask for AMD modifiers. · b7397bad

Bas Nieuwenhuizen authored Nov 13, 2020

The DCC_MAX_COMPRESSED_BLOCK has to contain one of
AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
fit in 1 bit.

Fix this cleanly while it is only in drm-next.

Fixes: 8ba16d59 ("drm/fourcc: Add AMD DRM modifiers.")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b7397bad

drm/amd/display: Add missing pflip irq for dcn2.0 · 52f6f16d

Alex Deucher authored Nov 13, 2020

If we have more than 4 displays we will run
into dummy irq calls or flip timout issues.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

52f6f16d