- 27 Feb, 2018 6 commits
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Rex Zhu authored
Clamp the clock index to a valid range when reading it back Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Roger He authored
Because ttm_bo_force_list_clean() is only called on two occasions: 1. By ttm_bo_evict_mm() during suspend. 2. By ttm_bo_clean_mm() when the driver unloads. On both cases we absolutely don't want any memory allocation failure. Signed-off-by:
Roger He <Hongbo.He@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Roger He authored
set TTM_OPT_FLAG_FORCE_ALLOC when we are servicing for page fault routine. for ttm_mem_global_reserve if in page fault routine, allow the gtt pages reservation always. because page fault routing already grabbed system memory and the allowance of this exception is harmless. Otherwise, it will trigger OOM killer. will be used later. v2: set the FORCE_ALLOC always v3: minor refine Signed-off-by:
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Roger He authored
for saving memory and more bit flag can be used in future Signed-off-by:
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Arnd Bergmann authored
In randconfig testing, we sometimes get this warning: drivers/gpu/drm/radeon/radeon_object.c: In function 'radeon_bo_create': drivers/gpu/drm/radeon/radeon_object.c:242:2: error: #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance thanks to write-combining [-Werror=cpp] #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ This is rather annoying since almost all other code produces no build-time output unless we have found a real bug. We already fixed this in the amdgpu driver in commit 31bb90f1 ("drm/amdgpu: shut up #warning for compile testing") by adding a CONFIG_COMPILE_TEST check last year and agreed to do the same here, but both Michel and I then forgot about it until I came across the issue again now. For stable kernels, as this is one of very few remaining randconfig warnings in 4.14. Cc: stable@vger.kernel.org Link: https://patchwork.kernel.org/patch/9550009/Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Christian König authored
To aid debugging set the page mapping during allocation instead of during VM faults. Signed-off-by:
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- 20 Feb, 2018 5 commits
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Alex Deucher authored
This reverts commit 1c331f75. Breaks resume on some systems. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=100759Signed-off-by:
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Christian König authored
We use our own backing store and don't need the shmem file. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Christian König authored
We use our own backing store and don't need the shmem file. Signed-off-by:
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Christian König authored
To be able to use DRI_PRIME with amdgpu and i915 we add all our fences only as exclusive ones. Disable that behavior when sharing between amdgpu itself cause it hinders concurrent execution. Signed-off-by:
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Christian König authored
Instead of the pin/unpin callback implement the attach/detach ones. Functional identical, but allows us access to the attachment. Signed-off-by:
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- 19 Feb, 2018 29 commits
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Alex Deucher authored
The logic has moved to cgs. mclk switching with DC at higher refresh rates should work. Reviewed-by:
Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by:
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Alex Deucher authored
Clamp the vblank period to 0 if the refresh rate is larger than 120 hz for non-DC. This allows us to remove the refresh rate checks from powerplay for mclk switching. Reviewed-by:
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Alex Deucher authored
If there are no displays attached, there is no reason to disable mclk switching. Fixes mclks getting set to high when there are no displays attached. Reviewed-by:
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Alex Deucher authored
If there are no displays attached, there is no reason to disable mclk switching. Fixes mclks getting set to high when there are no displays attached. Reviewed-by:
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Alex Deucher authored
Rather than open coding it. Reviewed-by:
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Corentin Labbe authored
All thoses headers are not used by any source files. Lets just remove them. Signed-off-by:
Corentin Labbe <clabbe@baylibre.com> Signed-off-by:
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Gustavo A. R. Silva authored
Currently, if amdgpu_vm_bo_update() fails, the returned error is being ignored. Fix this by properly checking _r_ after calling amdgpu_vm_bo_update. Also, remove redundant code just before label _error_. Addresses-Coverity-ID: 1464280 ("Unused value") Fixes: 0abc6878 ("drm/amdgpu: update VM PDs after the PTs") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by:
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Christian König authored
Updating the PASID is rather heavyweight and shouldn't be done all the time. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by:
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Leo (Sunpeng) Li authored
Previously, the number of software segmets per region was reduced to 16. This needs to be reflected in the sampling distance (increment) used when translating to the hardware format. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Vitaly Prosyak authored
Some refactoring and optimizations in color module. Added de gamma 2.2 & 2.4, also re gamma 2.2. Added interface for diagnostic for de gamma & de pq. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Eric Yang authored
Add basic logging for DPCD access. Does not print by default. Currently only prints first byte of the data accessed. Technical debt: Need to make it so that the entire data block accessed is printed. Also need to log address space that's not DPCD. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Tao authored
Brightness couldn't change when booting up in DC mode. It was because "psr_enabled" flag was not set to true before setting vsc packet revision, causing packet rev setup was skipped. Now instead of checking the psr flag, it checks if the DPCD_REV >= 1.2 and set the vsc packet revision. Signed-off-by:
Tao <xtao@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Eric Yang authored
We have an mst dock firmware that will emulate an EDID with bad checksum. v2: Tread -> Treat Signed-off-by:
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Ken Chalmers authored
Identical to the two entries above them. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Roman Li authored
Previously, FBC dynamic allocation relied on connector modes populated during dm init. This is only the case if DRM_FBDEV_EMULATION config flag is enabled. Moving fbc allocation from dm_late_init() to amdgpu_dm_connector_get_modes() where actual modes init happens. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Shirish Shankarappa <Shirish.S@amd.com> Acked-by:
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John Barberiz authored
HDMI HPD's generic solution makes the monitor patch code unnecessary so anything related has been removed. Signed-off-by:
John Barberiz <jbarberi@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
Skipping the first frame will prevent uncoooked values most of the time. However, in some unlikely cases, the second frame will be uncooked as well. Signed-off-by:
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Leo (Sunpeng) Li authored
Implement CRC for DCE8. Registers remain the same, so call DCE110 code directly. Signed-off-by:
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Leo (Sunpeng) Li authored
Clear up the logic, and enable programming truncation as a bit reduction mode. Signed-off-by:
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Leo (Sunpeng) Li authored
When user-mode is using 8bpc, the hardware represents it internally using a higher bit depth. This causes problems when comparing CRCs for color managment tests. We need to disable dithering as well, since it makes CRC values non-deterministic. It's easy to see why dithering needs to be disabled, The reason why truncation also needs to be enabled is better described with an example. Consider the folowing which tests the color transform matrix (CTM): Expected CRC = FB_A -> Degamma (Bypassed) -> CTM (Bypassed) | v Obtain CRC <- Regamma(Bypassed) Actual CRC = FB_B -> Degamma (Bypassed) -> CTM (0.5*Identity) | v Obtain CRC <- Regamma(Bypassed) FB_A contains a solid red color at half intensity (127 @ 8bpc) FB_B contains a solid red color at full intensity (255 @ 8bpc) We expect that Expected CRC = Actual CRC, but that's not the case. When the CTM is applied, the output is at half intensity, but also at a higher bit depth within hardware. i.e. 255/2 = 127.5: not representable in 8bpc, but can be at 10bpc. This causes the two CRC's to be different. The solution is to truncate the output bit depth to the same as input when enabling CRC capture. Since Linux only supports 8bpc, hard code that for now. Signed-off-by: -
Leo (Sunpeng) Li authored
We will need this to disable dither for CRC capture. Signed-off-by:
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Leo (Sunpeng) Li authored
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Leo (Sunpeng) Li authored
Hookup new color management functions into amdgpu_dm: - Notify DRM that we support CRTC color management during CRTC init - Call color management functions within atomic check to update dc states in preparation for a commit Signed-off-by:
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Leo (Sunpeng) Li authored
Implement color management functionalities within amdgpu_dm_color, and expose functions within amdgpu_dm.h. Signed-off-by:
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Leo (Sunpeng) Li authored
Also guard includes that we don't need. Signed-off-by:
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