- 06 Jun, 2019 40 commits
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David S. Miller authored
Robert Hancock says: ==================== Xilinx axienet driver updates (v5) This is a series of enhancements and bug fixes in order to get the mainline version of this driver into a more generally usable state, including on x86 or ARM platforms. It also converts the driver to use the phylink API in order to provide support for SFP modules. Changes since v4: -Use reverse christmas tree variable order ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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Robert Hancock authored
Convert this driver to use the phylink API rather than the legacy PHY API. This allows for better support for SFP modules connected using a 1000BaseX or SGMII interface. Signed-off-by:
Robert Hancock <hancock@sedsystems.ca> Signed-off-by:
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Robert Hancock authored
Currently the axienet driver requires the use of a second devicetree node, referenced by an axistream-connected attribute on the Ethernet device node, which contains the resources for the AXI DMA block used by the device. This setup is problematic for a use case we have where the Ethernet and DMA cores are behind a PCIe to AXI bridge and the memory resources for the nodes are injected into the platform devices using the multifunction device subsystem - it's not easily possible for the driver to obtain the platform-level resources from the linked device. In order to simplify that usage model, and simplify the overall use of this driver in general, allow for all of the resources to be kept on one node where the resources are retrieved using platform device APIs rather than device-tree-specific ones. The previous usage setup is still supported if the axistream-connected attribute is specified. Signed-off-by:
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Robert Hancock authored
The axienet driver requires the use of an axistream-connected attribute, but this isn't documented in the devicetree bindings. Document how this attribute is supposed to be used, including the upcoming change to make the usage of this attribute optional. Signed-off-by:
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Robert Hancock authored
This driver was previously using the parent node of the specified PHY node as the device node to register the MDIO bus on. Andrew Lunn pointed out this is wrong as the PHY node is potentially not even underneath the MDIO bus for the current device instance. Find the MDIO node explicitly by looking it up by name under the controller's device node instead. This could potentially break existing device trees if they don't use "mdio" as the name for the MDIO bus, but I did not find any with various searches and Xilinx's examples all use mdio as the name so it seems like this should be relatively safe. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Robert Hancock authored
The mdio child node for the MDIO bus is generally required when using this driver but was not documented other than being shown in the example. Document it as an optional (but usually required) parameter. Signed-off-by:
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Robert Hancock authored
On some platforms, such as iMX6 with PCIe devices, crashes or hangs can occur if the axienet device continues to perform DMA transfers after parent devices/busses have been shut down. Shut down the axienet interface during its shutdown callback in order to avoid this. Signed-off-by:
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Robert Hancock authored
Failing initialization on a missing MAC address property is excessive. We can just fall back to using a random MAC instead, which at least leaves the interface in a functioning state. Signed-off-by:
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Robert Hancock authored
It is possible that the interrupt handler fires and frees up space in the TX ring in between checking for sufficient TX ring space and stopping the TX queue in axienet_start_xmit. If this happens, the queue wake from the interrupt handler will occur before the queue is stopped, causing a lost wakeup and the adapter's transmit hanging. To avoid this, after stopping the queue, check again whether there is sufficient space in the TX ring. If so, wake up the queue again. Signed-off-by:
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Robert Hancock authored
Previously this driver only handled interrupts from the DMA RX and TX blocks, not from the Ethernet core itself. Add optional support for the Ethernet core interrupt, which is used to detect rx_missed and framing errors signalled by the hardware. In order to use this interrupt, a third interrupt needs to be specified in the device tree. Signed-off-by:
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Robert Hancock authored
Specify IRQF_SHARED to support shared interrupts. If the interrupt handler is called and the device is not indicating an interrupt, just return IRQ_NONE rather than spewing error messages. Signed-off-by:
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Robert Hancock authored
These registers are important for troubleshooting the state of the DMA cores. Signed-off-by:
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Robert Hancock authored
Add support for setting the RX and TX ring sizes for this driver using ethtool. Also increase the default RX ring size as the previous default was far too low for good performance in some configurations. Signed-off-by:
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Robert Hancock authored
The Xilinx DMA blocks each have their own reset register, but they both reset the entire DMA engine, so only one of them needs to be reset. Also, when stopping the device, we need to not just command the DMA blocks to stop, but wait for them to stop, and trigger a device reset to ensure that they are completely stopped. Signed-off-by:
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Robert Hancock authored
The MDIO clock divisor register setting was only applied on the initial startup when the driver was loaded. However, this setting is cleared when the device is reset, such as would occur when the interface was taken down and brought up again, and so the MDIO bus would be non-functional afterwards. Split up the MDIO bus setup and enable into separate functions and re-enable the bus after a device reset, to ensure that the MDIO registers are set properly. This also allows us to remove direct access to MDIO registers in xilinx_axienet_main.c and centralize them all in xilinx_axienet_mdio.c. Also, lock the MDIO bus lock around the device reset process, to avoid MDIO accesses from occurring while the MDIO is disabled during the reset. Signed-off-by:
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Robert Hancock authored
Since the MDIO is is brought up before the netdev is registered, it should be torn down after the netdev is removed. Otherwise, PHY accesses can potentially access freed MDIO bus references and cause a crash. Signed-off-by:
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Robert Hancock authored
This driver was previously always calculating the MDIO clock divisor (from AXI bus clock to MDIO bus clock) based on the CPU clock frequency, assuming that it is the same as the AXI bus frequency, but that simplistic method only works on the MicroBlaze platform. Add support for specifying the clock used for the device in the device tree using the clock framework. If the clock is specified then it will be used when calculating the clock divisor. The previous CPU clock detection method is left for backward compatibility if no clock is specified. Signed-off-by:
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Robert Hancock authored
This driver should now build on (at least) X86 and ARM platforms, so add them as supported platforms for the driver in Kconfig. Signed-off-by:
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Robert Hancock authored
The MDIO bus for this driver was being named using the result of of_address_to_resource on a node which may not have any resource on it, but the return value of that call was not checked so it was using some random value in the bus name. Change to name the MDIO bus based on the resource start of the actual Ethernet register block. Signed-off-by:
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Robert Hancock authored
This driver was using in_be32 and out_be32 IO accessors which do not exist on most platforms. Also, the use of big-endian accessors does not seem correct as this hardware is accessed over an AXI bus which, to the extent it has an endian-ness, is little-endian. Switch to standard ioread32/iowrite32 accessors. Signed-off-by:
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Robert Hancock authored
This driver was casting skb pointers to u32 and storing them as such in the DMA buffer descriptor, which is obviously broken on 64-bit. The area of the buffer descriptor being used is not accessed by the hardware and has sufficient room for a 32 or 64-bit pointer, so just store the skb pointer as such. Signed-off-by:
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Dinh Nguyen authored
On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from the Cyclone5 and Arria5: - The emac PHY setup bits are in separate registers. - The PTP reference clock select mask is different. - The register to enable the emac signal from FPGA is different. Thus, this patch creates a separate function for setting the phy modes on Arria10/Agilex/Stratix10. The separation is based a new DTS binding: "altr,socfpga-stmmac-a10-s10". Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org> Signed-off-by:
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Dinh Nguyen authored
Add the "altr,socfpga-stmmac-a10-s10" binding for Arria10/Agilex/Stratix10 implementation of the stmmac ethernet controller. On the Arria10, Agilex, and Stratix10 SoCs, there are a few differences from the Cyclone5 and Arria5: - The emac PHY setup bits are in separate registers. - The PTP reference clock select mask is different. - The register to enable the emac signal from FPGA is different. Because of these differences, the dwmac-socfpga glue logic driver will use this new binding to set the appropriate bits for PHY, PTP reference clock, and signal from FPGA. Signed-off-by: -
David S. Miller authored
Jakub Kicinski says: ==================== nfp: tls: add basic TX offload This series adds initial TLS offload support to the nfp driver. Only TX side is added for now. We need minor adjustments to the core tls code: - expose the per-skb fallback helper; - grow the driver context slightly; - add a helper to get to the driver state more easily. We only support TX offload for now, and only if all packets keep coming in order. For retransmissions we use the aforementioned software fallback, and in case there are local drops we completely give up on given TCP stream. This will obviously be improved soon, this patch set is the minimal, functional yet easily reviewable chunk. ==================== Signed-off-by: -
Jakub Kicinski authored
Count TX TLS packets: successes, out of order, and dropped due to missing record info. Make sure the RX and TX completion statistics don't share cache lines with TX ones as much as possible. With TLS stats they are no longer reasonably aligned. Signed-off-by:
Dirk van der Merwe <dirk.vandermerwe@netronome.com> Signed-off-by:
Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by:
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Dirk van der Merwe authored
This patch adds the functionality to add and delete TLS connections on the NFP, received from the kernel TLS callbacks. Make use of the common control message (CCM) infrastructure to propagate the kernel state to firmware. Signed-off-by:
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Dirk van der Merwe authored
Prepend connection handle to each transmitted TLS packet. For each connection, the driver tracks the next sequence number expected. If an out of order packet is observed, the driver calls into the TLS kernel code to reencrypt that particular skb. Signed-off-by:
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Dirk van der Merwe authored
While offloading TLS connections, drivers need to handle the case where out of order packets need to be transmitted. Other drivers obtain the entire TLS record for the specific skb to provide as context to hardware for encryption. However, other designs may also want to keep the hardware state intact and perform the out of order encryption entirely on the host. To achieve this, export the already existing software encryption fallback path so drivers could access this. Signed-off-by:
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Jakub Kicinski authored
Currently drivers have to ensure the alignment of their tls state structure, which leads to unnecessary layers of getters and encapsulated structures in each driver. Simplify all this by marking the driver state as aligned (driver_state members are currently aligned, so no hole is added, besides ALIGN in TLS_OFFLOAD_CONTEXT_SIZE_RX/TX would reserve this extra space, anyway.) With that we can add a common accessor to the core. Signed-off-by:
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Jakub Kicinski authored
8 bytes of driver state has been enough so far, but for drivers which have to store 8 byte handle it's no longer practical to store the state directly in the context. Drivers generally don't need much extra state on RX side, while TX side has to be tracking TCP sequence numbers. Split the lengths of max driver state size on RX and TX. The struct tls_offload_context_tx currently stands at 616 bytes and struct tls_offload_context_rx stands at 368 bytes. Upcoming work will consume extra 8 bytes in both for kernel-driven resync. This means that we can bump TX side to 16 bytes and still fit into the same number of cache lines but on RX side we would be 8 bytes over. Signed-off-by:
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Jakub Kicinski authored
Subsequent patches will add support for more TX metadata fields. Prepare for this by handling an additional double word - firmware handle as metadata type 7. Signed-off-by:
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Jakub Kicinski authored
Add FW ABI defines and code for basic init of TLS offload. Signed-off-by:
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Jakub Kicinski authored
Parse TLV containing a bitmask of supported crypto operations. The TLV contains a capability bitmask (supported operations) and enabled bitmask. Each operation describes the crypto protocol quite exhaustively (protocol, AEAD, direction). Signed-off-by:
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Jakub Kicinski authored
FW may prefer to handle some communication via a mailbox or the vNIC may simply not have a control queue (VFs). Add a way of exchanging ccm-compatible messages via a mailbox. Signed-off-by:
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Jakub Kicinski authored
Parse the mailbox TLV. When control message queue is not available we can fall back to passing the control messages via the vNIC mailbox. Signed-off-by:
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Jakub Kicinski authored
We will need to release the bar lock from a workqueue so move from a mutex to a semaphore. This lock should not be too hot. Unfortunately semaphores don't have lockdep support. Signed-off-by:
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Jakub Kicinski authored
Currently if we need to modify the head of the skb and allocation fails we would free the skb and not increment the error counter. Make sure all errors are counted. Signed-off-by:
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Robert Hancock authored
Add 1000BaseX to the link modes which are detected based on the MII_ESTATUS register as per 802.3 Clause 22. This allows PHYs which support 1000BaseX to work properly with drivers using phylink. Previously 1000BaseX support was not detected, and if that was the only mode the PHY indicated support for, phylink would refuse to attach it due to the list of supported modes being empty. Signed-off-by:
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YueHaibing authored
Fix sparse warning: drivers/net/ethernet/mscc/ocelot_ace.c:96:3: warning: symbol 'vcap_data_t' was not declared. Should it be static? 'vcap_data_t' never used so can be removed Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Fabio Estevam authored
When a valid MAC address is not found the current messages are shown: fec 2188000.ethernet (unnamed net_device) (uninitialized): Invalid MAC address: 00:00:00:00:00:00 fec 2188000.ethernet (unnamed net_device) (uninitialized): Using random MAC address: aa:9f:25:eb:7e:aa Since the network device has not been registered at this point, it is better to use dev_err()/dev_info() instead, which will provide cleaner log messages like these: fec 2188000.ethernet: Invalid MAC address: 00:00:00:00:00:00 fec 2188000.ethernet: Using random MAC address: aa:9f:25:eb:7e:aa Tested on a imx6dl-pico-pi board. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
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