- 15 Sep, 2020 6 commits
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Stephan Gerhold authored
The "sound" node in apq8016-sbc.dtsi references memory regions provided by the SoC and should be therefore declared in msm8916.dtsi. Additionally, the machine driver used for the "qcom,apq8016-sbc-sndcard" compatible also works on other MSM8916 devices (provided that audio routing is set up properly). It is not really specific to apq8016-sbc. Simplify setting up sound on other boards by moving the common part to msm8916.dtsi. This also allows referencing the node by the label, so that we can eventually drop the "soc" node entirely from the board-specific device tree part and use labels exclusively. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200720085406.6716-3-stephan@gerhold.netSigned-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Stephan Gerhold authored
apq8016-sbc.dtsi overrides several properties that are already the default in msm8916.dtsi. Remove these to simplify the device tree a bit. Signed-off-by:
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Dmitry Baryshkov authored
Currently sm8250.dtsi only defines default debug uart. Port rest uart nodes from the downstream dtsi file. Acked-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200909103238.149761-1-dmitry.baryshkov@linaro.orgSigned-off-by:
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satya priya authored
Add the necessary pinctrl, interrupt property and a suitable sleep config to support Bluetooth wakeup feature. GPIO mode is configured in sleep state to drive the RTS/RFR line low. If QUP function is selected in sleep state, UART RTS/RFR is pulled high during suspend and BT SoC not able to send wakeup bytes. Tested-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
satya priya <skakit@codeaurora.org> Link: https://lore.kernel.org/r/1600091917-7464-4-git-send-email-skakit@codeaurora.orgSigned-off-by:
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satya priya authored
Add the necessary pinctrl, interrupt property and a suitable sleep config to support Bluetooth wakeup feature. GPIO mode is configured in sleep state to drive the RTS/RFR line low. If QUP function is selected in sleep state, UART RTS/RFR is pulled high during suspend and BT SoC not able to send wakeup bytes. Reviewed-by:
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satya priya authored
Remove output-high from CTS and TX as this is not really required. During bringup to fix transfer failures this was added to match with console uart settings. Probably some boot loader config was missing then. As it is working fine now, remove it. Signed-off-by:
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- 14 Sep, 2020 3 commits
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Stephen Boyd authored
Some trogdor board variants only have one USB port, so add a couple labels to these ports so we can modify them later. Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200914232218.658664-1-swboyd@chromium.orgSigned-off-by:
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Łukasz Patron authored
Also add a space after '=' while at it. Tested-by:
Konrad Dybcio <konradybcio@gmail.com> Signed-off-by:
Łukasz Patron <priv.luk@gmail.com> Link: https://lore.kernel.org/r/20200725082417.8507-1-priv.luk@gmail.comSigned-off-by:
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Stephen Boyd authored
The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two where the second cell is the irq flags. Drop the second cell to match the binding. Cc: Kalyan Thota <kalyan_t@codeaurora.org> Cc: Harigovindan P <harigovi@codeaurora.org Fixes: a3db7ad1 ("arm64: dts: sc7180: add display dt nodes") Signed-off-by:
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- 13 Sep, 2020 11 commits
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Gokul Sriram Palanisamy authored
Document the new device-tree bindings for boards HK10-C1 and HK10-C2 based on ipq8074 SoC. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Link: https://lore.kernel.org/r/1596706332-12957-2-git-send-email-gokulsri@codeaurora.orgSigned-off-by:
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Kathiravan T authored
IPQ8074 has A53 cores, so lets use the corresponding PMU compatible. Signed-off-by:
Kathiravan T <kathirav@codeaurora.org> Link: https://lore.kernel.org/r/1597642116-15902-1-git-send-email-kathirav@codeaurora.orgSigned-off-by:
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Kathiravan T authored
Add A53 PLL, APCS clock, RPM Glink, RPM message RAM, cpu-opp-table, SMPA2 regulator to enable the cpu frequency on IPQ6018. Co-developed-by:
Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by:
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Kathiravan T authored
Add the mailbox compatible for the IPQ6018 SoC. Acked-by:
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Adrian Schmutzler authored
While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by:
Adrian Schmutzler <freifunk@adrianschmutzler.de> Link: https://lore.kernel.org/r/20200830200845.1771-1-freifunk@adrianschmutzler.deSigned-off-by:
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Kathiravan T authored
Enable watchdog support for the IPQ8074 SoCs. Signed-off-by:
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Jonathan Marek authored
Downstream has this clock as 32000 rate, but testing shows it is close to 32768. Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200903215923.14314-1-jonathan@marek.caSigned-off-by:
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Douglas Anderson authored
Add a new SKU variant. This is a pick from the downstream tree that is the current source of truth for this platform. Link: https://crrev.com/c/2386997Signed-off-by:
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Venkata Lakshmi Narayana Gubba authored
Removed voting for RPMH_RF_CLK2 which is not required as it is getting managed by BT SoC through SW_CTRL line. Signed-off-by:
Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org> Link: https://lore.kernel.org/r/1599734980-22580-1-git-send-email-gubbaven@codeaurora.orgSigned-off-by:
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Dmitry Baryshkov authored
Add device tree nodes describing used i2c busses according to the dts found in msm-4.19 tree. Signed-off-by:
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Dmitry Baryshkov authored
Signed-off-by:
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- 12 Sep, 2020 1 commit
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Amit Pundir authored
Add initial dts support for Xiaomi Poco F1 (Beryllium). This initial support is based on upstream Dragonboard 845c (sdm845) device. With this dts, Beryllium boots AOSP up to ADB shell over USB-C. Supported functionality includes UFS, USB-C (peripheral), microSD card and Vol+/Vol-/power keys. Bluetooth should work too but couldn't be verified from adb command line, it is verified when enabled from UI with few WIP display patches. Just like initial db845c support, initializing the SMMU is clearing the mapping used for the splash screen framebuffer, which causes the device to hang during boot and recovery needs a hard power reset. This can be worked around using: fastboot oem select-display-panel none To switch ON the display back run: fastboot oem select-display-panel But this only works on Beryllium devices running bootloader version BOOT.XF.2.0-00369-SDM845LZB-1 that shipped with Android-9 based release. Newer bootloader version do not support switching OFF the display panel at all. Reviewed-by:Amit Pundir <amit.pundir@linaro.org> Link: https://lore.kernel.org/r/1599840940-18144-1-git-send-email-amit.pundir@linaro.orgSigned-off-by:
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- 10 Sep, 2020 13 commits
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Krishna Manikandan authored
Move the bus clock to mdp device node,in order to facilitate bus band width scaling on sc7180 target. The parent device MDSS will not vote for bus bw, instead the vote will be triggered by mdp device node. Since a minimum vote is required to turn on bus clock, move the clock node to mdp device from where the votes are requested. This patch has dependency on the below series https://patchwork.kernel.org/patch/11468783/Reviewed-by:
Rob Clark <robdclark@chromium.org> Signed-off-by:
Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1594899334-19772-2-git-send-email-kalyan_t@codeaurora.orgSigned-off-by:
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Pradeep P V K authored
Add the bandwidth domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Signed-off-by:
Pradeep P V K <ppvk@codeaurora.org> Signed-off-by:
Shaik Sajida Bhanu <sbhanu@codeaurora.org> Link: https://lore.kernel.org/r/1597646464-1863-1-git-send-email-sbhanu@codeaurora.orgSigned-off-by:
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Matthias Kaehlcke authored
The 'sustainable_power' attribute provides an estimate of the sustained power that can be dissipated at the desired control temperature. One could argue that this value is not necessarily the same for all devices with the same SoC, which may have different form factors or thermal designs. However there are reasons to specify a (default) value at SoC level for SC7180: most importantly, if no value is specified at all the power_allocator thermal governor (aka 'IPA') estimates a value, using the minimum power of all cooling devices of the zone, which can result in overly aggressive thermal throttling. For most devices an approximate conservative value should be more useful than the minimum guesstimate of power_allocator. Devices that need a different value can overwrite it in their <device>.dts. Also the thermal zones for SC7180 have a high level of granularity (essentially one for each function block), which makes it more likely that the default value just works for many devices. The values correspond to 1901 MHz for the big cores, and 1804 MHz for the small cores. The values were determined by limiting the CPU frequencies to different max values and launching a bunch of processes that cause high CPU load ('while true; do true; done &' is simple and does a good job). A frequency is deemed sustainable if the CPU temperatures don't rise (consistently) above the second trip point ('control temperature', 95 degC in this case). Once the highest sustainable frequency is found, the sustainable power can be calculated by multiplying the energy consumption per core at this frequency (which can be found in /sys/kernel/debug/energy_model/) with the number of cores that are specified as cooling devices. The sustainable frequencies were determined at room temperature on a device without heat sink or other passive cooling elements. Reviewed-by: -
Rajendra Nayak authored
Add the OPP tables in order to be able to vote on the performance state of a power-domain Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1598970026-7199-6-git-send-email-rnayak@codeaurora.orgSigned-off-by:
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Rajendra Nayak authored
Add the OPP tables in order to be able to vote on the performance state of a power-domain. Signed-off-by:
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Krishna Manikandan authored
This change adds the interconnect bindings to the MDSS node. This will establish Display to DDR path for bus bandwidth voting. Reviewed-by:
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Taniya Das authored
Update the clock controller nodes for Low power audio subsystem functionality. Reviewed-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1596305615-5894-2-git-send-email-tdas@codeaurora.orgSigned-off-by:
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Manivannan Sadhasivam authored
Add gpio-line-names for the GPIO pins exposed by PM8150, PM8150B and PM8150L PMIC nodes. Signed-off-by:
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Manivannan Sadhasivam authored
Add gpio-line-names property for QRB5165 RB5 board for naming all GPIOs exposed by TLMM block. Signed-off-by:
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Manivannan Sadhasivam authored
Only User4, WLAN and BT LEDs are added for now. These GPIOs are coming from PM8150. Rest are coming from LPG block which is not supported yet! Signed-off-by:
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Manivannan Sadhasivam authored
Add basic devicetree support for Qualcomm Technologies, Inc. Robotics RB5 platform. This board is one of the 96Boards CE platform targeted for Robotics usecases from Qualcomm. This basic devicetree support includes regulators, onboard debug UART, I2C, SPI, and UFS support. Co-developed-by:
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Manivannan Sadhasivam authored
The UART12 node has been mistakenly mentioned as UART2. Let's fix that for both SM8250 SoC and MTP board and also add pinctrl definition for it. Fixes: 60378f1a ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Signed-off-by:
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Manivannan Sadhasivam authored
Document the SM8250 SoC binding and also the boards using it. Signed-off-by:
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- 31 Aug, 2020 1 commit
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Rob Clark authored
This is essentialy a squash of a bunch of history of trogdor and lazor dt updates from the chromium kernel tree. I don't claim any credit other than wanting to more easily boot upstream kernel on these devices. I've tried to add cc tags for all the original authors. Cc: Stephen Boyd <swboyd@chromium.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Atul Dhudase <adhudase@codeaurora.org> Cc: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org> Cc: Evan Green <evgreen@chromium.org> Cc: Cheng-Yi Chiang <cychiang@chromium.org> Cc: Ajit Pandey <ajitp@codeaurora.org> Cc: Alexandru Stan <amstan@chromium.org> Cc: Sujit Kautkar <sujitka@chromium.org> Signed-off-by:
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- 30 Aug, 2020 5 commits
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Sai Prakash Ranjan authored
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct the size and fix copy paste mistake carried over from SDM845. Reviewed-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/20200818145514.16262-1-saiprakash.ranjan@codeaurora.orgSigned-off-by:
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Jonathan Marek authored
Constants were used to allow merging separately from the dt-bindings, switch to symbolic names now that dt-bindings have landed. Signed-off-by:
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Jonathan Marek authored
Constants were used to allow merging separately from the dt-bindings, switch to symbolic names now that dt-bindings have landed. Signed-off-by:
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Jonathan Marek authored
The compatible for hsphy has out of place indentation, and the assigned clock rate for GCC_USB30_PRIM_MASTER_CLK is incorrect, the clock doesn't support a rate of 150000000. Use a rate of 200000000 to match downstream. Fixes: b33d2868 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes") Signed-off-by:
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Tanmay Shah authored
This node defines alternate DP HPD functionality of GPIO. Reviewed-by:
Tanmay Shah <tanmay@codeaurora.org> Link: https://lore.kernel.org/r/20200818033657.16074-1-tanmay@codeaurora.orgSigned-off-by:
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