- 31 Jul, 2019 40 commits
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Kevin Wang authored
1. Unified feature enable status format in sysfs 2. Rename ppfeature to pp_features to adapt other pp sysfs node name 3. this function support all asic, not asic related function. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
Rui Huang <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
this function is not ip or asic related function, so move it to top level as public api in smu. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Kevin Wang authored
add smu_get_feature_name support in smu. Signed-off-by:
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Kevin Wang authored
add smu_get_message_name support in smu. Signed-off-by:
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Kevin Wang authored
move some enum type (message, feature, clock) to smu_types.h. these types is too long in amdgpu_smu.h, and not clearly. Signed-off-by:
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Joseph Greathouse authored
Units in the GDS block default to allowing all VMIDs access to all entries. Disable shader access to the GDS, GWS, and OA blocks from all compute and gfx VMIDs by default. For compute, HWS firmware will set up the access bits for the appropriate VMID when a compute queue requires access to these blocks. The driver will handle enabling access on-demand for graphics VMIDs. Leaving VMID0 with full access because otherwise HWS cannot save or restore values during task switch. v2: Fixed code and comment styling. Signed-off-by:
Joseph Greathouse <Joseph.Greathouse@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Thong Thai authored
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by:
Thong Thai <thong.thai@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Alex Deucher authored
Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Add restriction to dissallow GTT domain if the relevant BO doesn't have USWC flag set to avoid the APU hang scenario. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Alex Deucher authored
The PCI revision id determines the sku. Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
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Alex Deucher authored
When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by:
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Alex Deucher authored
This sets the SMU into the proper state for various operations (shutdown, unload, GPU reset, etc.). Reviewed-by:
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Alex Deucher authored
This sets the SMU into the proper state for various operations (shutdown, unload, GPU reset, etc.). Reviewed-by:
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Alex Deucher authored
This sets the SMU into the proper state for various operations (shutdown, unload, GPU reset, etc.). Reviewed-by:
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Alex Deucher authored
Some asics (APUs) don't have this callback so we want to return success. Avoids spurious error messages on APUs. Reviewed-by:
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Alex Deucher authored
This is required for certain cases such as various GPU resets (mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into the appropriate state for when the hw is re-initialized. Reviewed-by:
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Alex Deucher authored
Navi uses either mode1 or baco depending on various conditions. Reviewed-by:
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Alex Deucher authored
APUs only support mode2 reset. dGPUs use either mode1 or baco depending on various conditions. Reviewed-by:
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Alex Deucher authored
VI always uses the legacy pci based reset. Reviewed-by:
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Alex Deucher authored
CIK always uses the legacy pci based reset. Reviewed-by:
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Alex Deucher authored
SI always uses the legacy pci based reset. Reviewed-by:
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Alex Deucher authored
Sometimes the driver may have to behave differently depending on the method we are using to reset the GPU. Reviewed-by:
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Evan Quan authored
Move SMU irq handler register to sw_init as that's totally software related. Otherwise, it will prevent SMU reset working. Signed-off-by:
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Evan Quan authored
DPM state relates are not supported on the new SW SMU ASICs. But still it's not OK to trigger null pointer dereference on accessing them. Signed-off-by:
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Evan Quan authored
Add checking for possible invalid input and null pointer. And drop redundant code. Signed-off-by:
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Shirish S authored
enables gpu_vm_support in dm and adds AMDGPU_GEM_DOMAIN_GTT as supported domain v2: Move BO placement logic into amdgpu_display_supported_domains v3: Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains. v4: amdgpu_bo_validate_uswc moved to sepperate patch. Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
This verifies we don't add GTT as allowed domain for APUs when USWC is disabled. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in amdgpu_bo_do_create into standalone helper so it can be reused in other functions. v4: Switch to return bool. v5: Fix typos. Signed-off-by:
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Andrey Grodzovsky authored
HW requires for caching to be unset for scanout BO mappings when the BO placement is in GTT memory. Usually the flag to unset is passed from user mode but for FB mode this was missing. v2: Keep all BO placement logic in amdgpu_display_supported_domains Suggested-by:
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Jonathan Kim authored
monitor xgmi errors via mc pie status through fica registers. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
Kent Russell <Kent.Russell@amd.com> Signed-off-by:
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Jonathan Kim authored
adding perfmon and fica atomic operations to adhere to data fabrics finite state machine requirements for indirect register access. Signed-off-by:
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Jay Cornwall authored
Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Acked-by:
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Jay Cornwall authored
Previously submitted code was taken from an incorrect branch and was non-functional. Cc: Oak Zeng <oak.zeng@amd.com> Signed-off-by:
Oak Zeng <oak.zeng@amd.com> Signed-off-by:
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Jay Cornwall authored
If the trap is entered due to MODE.DEBUG_EN=1 and SAVECTX is raised concurrently the handler cannot identify the source of the exception. This causes the debugger to lose single step exception notification when a context save request arrives at the same time. When MODE.DEBUG_EN=1 and STATUS.HALT=0 (exception not already handled) jump to the second-level trap handler upon entering the trap. The second-level trap will set STATUS.HALT=1 and return to the shader. If SAVECTX was raised then control flow will return to the trap, which will then handle the context save request. Cc: Tony Tye <tony.tye@amd.com> Cc: Laurent Morichetti <laurent.morichetti@amd.com> Cc: Qingchuan Shi <qingchuan.shi@amd.com> Signed-off-by:
Laurent Morichetti <laurent.morichetti@amd.com> Signed-off-by:
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Jay Cornwall authored
When a wavefront raises TRAPSTS.XNACK_ERROR with STATUS.ALLOW_REPLAY=0 subsequent memory instructions have undefined behavior. In practice SQC stores continue to work but TCP stores do not. Context save is permitted to fail after XNACK error because the wavefront will be halted and subsequently terminated. However the debugger has an interest in retrieving the wavefront VGPR/LDS state. Detect the out-of-spec case and use SQC stores during context save in place of TCP stores. Signed-off-by:
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tiancyin authored
navi14 share same PTE format with navi10. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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James Zhu authored
Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Kevin Wang authored
in this patch, drm/amd/powerplay: add callback function of get_thermal_temperature_range the driver missed temperature granularity change on other temperature. Signed-off-by:
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Evan Quan authored
Drop redundant check, duplicate check, duplicate setting and fix the return value. Signed-off-by:
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Evan Quan authored
Honor the 'dpm' module parameter setting on SW SMU routine as what we did on previous ASICs. SMU FW loading is still proceeded even with "dpm=0". Signed-off-by:
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