1. 28 May, 2014 2 commits
  2. 27 May, 2014 5 commits
  3. 20 May, 2014 30 commits
  4. 19 May, 2014 1 commit
    • Dave Airlie's avatar
      Merge tag 'drm-intel-fixes-2014-05-16' of git://anongit.freedesktop.org/drm-intel into drm-fixes · 4ba4801d
      Dave Airlie authored
      Intel fixes for regressions, black screens and hangs, for 3.15.
      
      * tag 'drm-intel-fixes-2014-05-16' of git://anongit.freedesktop.org/drm-intel:
        drm/i915: Increase WM memory latency values on SNB
        drm/i915: restore backlight precision when converting from ACPI
        drm/i915: Use the first mode if there is no preferred mode in the EDID
        drm/i915/dp: force eDP lane count to max available lanes on BDW
        drm/i915/vlv: reset VLV media force wake request register
        drm/i915/SDVO: For sysfs link put directory and target in correct order
        drm/i915: use lane count and link rate from VBT as minimums for eDP
        drm/i915: clean up VBT eDP link param decoding
        drm/i915: consider the source max DP lane count too
      4ba4801d
  5. 16 May, 2014 1 commit
    • Mark Salter's avatar
      arm64: fix pud_huge() for 2-level pagetables · 4797ec2d
      Mark Salter authored
      The following happens when trying to run a kvm guest on a kernel
      configured for 64k pages. This doesn't happen with 4k pages:
      
        BUG: failure at include/linux/mm.h:297/put_page_testzero()!
        Kernel panic - not syncing: BUG!
        CPU: 2 PID: 4228 Comm: qemu-system-aar Tainted: GF            3.13.0-0.rc7.31.sa2.k32v1.aarch64.debug #1
        Call trace:
        [<fffffe0000096034>] dump_backtrace+0x0/0x16c
        [<fffffe00000961b4>] show_stack+0x14/0x1c
        [<fffffe000066e648>] dump_stack+0x84/0xb0
        [<fffffe0000668678>] panic+0xf4/0x220
        [<fffffe000018ec78>] free_reserved_area+0x0/0x110
        [<fffffe000018edd8>] free_pages+0x50/0x88
        [<fffffe00000a759c>] kvm_free_stage2_pgd+0x30/0x40
        [<fffffe00000a5354>] kvm_arch_destroy_vm+0x18/0x44
        [<fffffe00000a1854>] kvm_put_kvm+0xf0/0x184
        [<fffffe00000a1938>] kvm_vm_release+0x10/0x1c
        [<fffffe00001edc1c>] __fput+0xb0/0x288
        [<fffffe00001ede4c>] ____fput+0xc/0x14
        [<fffffe00000d5a2c>] task_work_run+0xa8/0x11c
        [<fffffe0000095c14>] do_notify_resume+0x54/0x58
      
      In arch/arm/kvm/mmu.c:unmap_range(), we end up doing an extra put_page()
      on the stage2 pgd which leads to the BUG in put_page_testzero(). This
      happens because a pud_huge() test in unmap_range() returns true when it
      should always be false with 2-level pages tables used by 64k pages.
      This patch removes support for huge puds if 2-level pagetables are
      being used.
      Signed-off-by: default avatarMark Salter <msalter@redhat.com>
      [catalin.marinas@arm.com: removed #ifndef around PUD_SIZE check]
      Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
      Cc: <stable@vger.kernel.org> # v3.11+
      4797ec2d
  6. 15 May, 2014 1 commit
    • John David Anglin's avatar
      parisc: Improve LWS-CAS performance · c776cd89
      John David Anglin authored
      The attached change significantly improves the performance of the LWS-CAS code
      in syscall.S.
      This allows a number of packages to build (e.g., zeromq3, gtest and libxs)
      that previously failed because slow LWS-CAS performance under contention. In
      particular, interrupts taken while the lock was taken degraded performance
      significantly.
      
      The change does the following:
      
      1) Disables interrupts around the CAS operation, and
      2) Changes the loads and stores to use the ordered completer, "o", on
      PA 2.0. "o" and "ma" with a zero offset are equivalent. The latter is
      accepted on both PA 1.X and 2.0.
      
      The use of ordered loads and stores probably makes no difference on all
      existing hardware, but it seemed pedantically correct. In particular, the CAS
      operation must complete before LDCW lock is released. As written before, a
      processor could reorder the operations.
      
      I don't believe the period interrupts are disabled is long enough to
      significantly increase interrupt latency. For example, the TLB insert code is
      longer. Worst case is a memory fault in the CAS operation.
      Signed-off-by: default avatarJohn David Anglin <dave.anglin@bell.net>
      Cc: stable@vger.kernel.org # 3.13+
      Signed-off-by: default avatarHelge Deller <deller@gmx.de>
      c776cd89