- 18 Oct, 2018 20 commits
-
-
Stephen Boyd authored
* clk-fixed-rate-remove: clk: fixed-rate: fix of_node_get-put imbalance * clk-qcom-cleanup: clk: qcom: Remove unused arrays in SDM845 GCC
-
Stephen Boyd authored
Merge branches 'clk-imx6-mmdc', 'clk-qcom-krait', 'clk-rockchip' and 'clk-smp2s11-match' into clk-next - iMX6 MMDC clks - Qualcomm Krait CPU clk support * clk-imx6-mmdc: clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock clk: imx6ul: add mmdc1 ipg clock * clk-qcom-krait: clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions * clk-rockchip: clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call clk: rockchip: use the newly added clock-id for hdmi on RK3066 clk: rockchip: add clock-id for HCLK_HDMI on rk3066 clk: rockchip: fix wrong mmc sample phase shift for rk3328 clk: rockchip: improve rk3288 pll rates for better hdmi output * clk-smp2s11-match: clk: s2mps11: Add used attribute to s2mps11_dt_match clk: s2mps11: Fix matching when built as module and DT node contains compatible
-
Stephen Boyd authored
Merge branches 'clk-actions-reset', 'clk-imx7-init-critical', 'clk-mmp2-ids' and 'clk-at91-pmc-rework' into clk-next - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs - Rework at91 PMC clock driver for new DT bindings * clk-actions-reset: clk: actions: Add Actions Semi S900 SoC Reset Management Unit support clk: actions: Add Actions Semi S700 SoC Reset Management Unit support clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support dt-bindings: reset: Add binding constants for Actions Semi S900 RMU dt-bindings: reset: Add binding constants for Actions Semi S700 RMU dt-bindings: clock: Add reset controller bindings for Actions Semi Owl SoCs clk: actions: Cache regmap info in private clock descriptor * clk-imx7-init-critical: clk: imx7d: remove CLK_IS_CRITICAL flag for arm_a7_root_clk clk: imx: cpu clock should be always critical clk: imx: imx7d: remove clks_init_on array clk: imx: imx7d: remove unnecessary clocks from clks_init_on array * clk-mmp2-ids: clk: mmp2: fix the clock id for sdh2_clk and sdh3_clk * clk-at91-pmc-rework: clk: at91: move DT compatibility code to its own file clk: at91: add at91sam9rl PMC driver clk: at91: add at91sam9x5 PMCs driver clk: at91: add at91sam9260 PMC driver clk: at91: add sama5d2 PMC driver clk: at91: add sama5d4 pmc driver clk: at91: add new DT lookup function dt-bindings: clk: at91: Document new PMC binding clk: at91: add pmc_data struct and helpers clk: at91: allow clock registration from C code clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() clk: at91: audio-pll: separate registration from DT parsing clk: at91: h32mx: separate registration from DT parsing clk: at91: generated: SSCs don't have a gclk clk: at91: audio-pll: fix audio pmc type
-
Stephen Boyd authored
- Nvidia Tegra clk driver MBIST workaround fix - clk_bulk_get_all() API and friends to get all the clks for a device * clk-tegra: clk: tegra210: Include size.h for compilation ease clk: tegra: Fixes for MBIST work around clk: tegra: probe deferral error reporting * clk-bulk-get-all: clk: add managed version of clk_bulk_get_all clk: add new APIs to operate on all available clocks clk: bulk: add of_clk_bulk_get()
-
Stephen Boyd authored
- Ingenic jz4725b CGU * clk-ingenic-jz4725b: clk: Add Ingenic jz4725b CGU driver dt-bindings: clock: Add jz4725b-cgu.h header dt-bindings: clock: ingenic: Explicitly list compatible strings clk: ingenic: Add proper Kconfig entries
-
Stephen Boyd authored
- Qualcomm QCS404 GCC support * clk-qcom-qcs404: clk: qcom: gcc: Add global clock controller driver for QCS404 clk: qcom: Export clk_alpha_pll_configure()
-
Stephen Boyd authored
- Qualcomm SDM660 GCC support * clk-qcom-sdm660: clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add Global Clock controller (GCC) driver for SDM660
-
Stephen Boyd authored
- Hisilicon 3670 SoC support * clk-samsung: dt-bindings: clock: samsung: Add SPDX license identifiers clk: samsung: Use clk_hw API for calling clk framework from clk notifiers clk: samsung: exynos5420: Enable PERIS clocks for suspend clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420 clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend clk: samsung: Remove obsolete code for Exynos4412 ISP clocks clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume clk: samsung: exynos5420: Use generic helper for handling suspend/resume clk: samsung: exynos4: Use generic helper for handling suspend/resume clk: samsung: Add support for setting registers state before suspend clk: samsung: exynos5250: Use generic helper for handling suspend/resume clk: samsung: s5pv210: Use generic helper for handling suspend/resume clk: samsung: s3c64xx: Use generic helper for handling suspend/resume clk: samsung: s3c2443: Use generic helper for handling suspend/resume clk: samsung: s3c2412: Use generic helper for handling suspend/resume clk: samsung: s3c2410: Use generic helper for handling suspend/resume clk: samsung: Remove excessive include * clk-hisi3670: clk: hisilicon: Add clock driver for Hi3670 SoC dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk * clk-at91-div-0: clk: at91: Fix division by zero in PLL recalc_rate()
-
Stephen Boyd authored
* clk-ti: clk: ti: Prepare for remove of OF node name clk: Clean up suspend/resume coding style clk: ti: Add functions to save/restore clk context clk: clk: Add clk_gate_restore_context function clk: Add functions to save/restore clock context en-masse clk: ti: dra7: add new clkctrl data clk: ti: dra7xx: rename existing clkctrl data as compat data clk: ti: am43xx: add new clkctrl data for am43xx clk: ti: am43xx: rename existing clkctrl data as compat data clk: ti: am33xx: add new clkctrl data for am33xx clk: ti: am33xx: rename existing clkctrl data as compat data clk: ti: clkctrl: replace dashes from clkdm name with underscore clk: ti: clkctrl: support multiple clkctrl nodes under a cm node dt-bindings: clock: dra7xx: add clkctrl indices for new data layout dt-bindings: clock: am43xx: add clkctrl indices for new data layout dt-bindings: clock: am33xx: add clkctrl indices for new data layout
-
Stephen Boyd authored
- TI SCI clks on K3 SoCs * clk-k3-tisci: clk: keystone: add missing MODULE_LICENSE clk: keystone: Enable TISCI clocks if K3_ARCH
-
Stephen Boyd authored
Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', 'clk-mvebu-dup' and 'clk-davinci' into clk-next - S2RAM support for Marvell mvebu periph clks * clk-mvebu-periph-pm: clk: mvebu: armada-37xx-periph: add suspend/resume support clk: mvebu: armada-37xx-periph: save the IP base address in the driver data * clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit * clk-allwinner: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position * clk-mvebu-dup: clk: mvebu: ap806: Remove superfluous of_clk_add_provider * clk-davinci: clk: davinci: kill davinci_clk_reset_assert/deassert()
-
Stephen Boyd authored
- Qualcomm SDM845 camera clock controller * clk-qcom-sdm845-camcc: clk: qcom: Add camera clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Camera clock bindings * clk-mtk-unused: clk: mediatek: remove unused array audio_parents
-
Stephen Boyd authored
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
-
Stephen Boyd authored
- Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds * clk-dt-name: clk: Convert to using %pOFn instead of device_node.name * clk-ti-of-node: clk: ti: fix OF child-node lookup * clk-sa: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe reset: hisilicon: fix potential NULL pointer dereference clk: cdce925: release child device nodes clk: qcom: clk-branch: Use true and false for boolean values
-
Stephen Boyd authored
Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', 'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 * clk-spdx: clk: mvebu: use SPDX-License-Identifier clk: renesas: Convert to SPDX identifiers clk: renesas: use SPDX identifier for Renesas drivers clk: s2mps11,s3c64xx: Add SPDX license identifiers clk: max77686: Add SPDX license identifiers * clk-qcom-dfs: clk: qcom: Allocate space for NULL terimation in DFS table clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845 clk: qcom: Add support for RCG to register for DFS * clk-smp2s11-include: clk: s2mps11: Use existing defines from bindings for clock IDs * clk-qcom-8996-missing: clk: qcom: Add some missing gcc clks for msm8996 * clk-qcom-qspi: clk: qcom: Add qspi (Quad SPI) clocks for sdm845 clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
-
Evan Green authored
This change removes a parent map and parent name array that appear to be completely unreferenced. Signed-off-by:
Evan Green <evgreen@chromium.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
-
Alan Tull authored
When the fixed rate clock is created by devicetree, of_clk_add_provider is called. Add a call to of_clk_del_provider in the remove function to balance it out. Signed-off-by:
Alan Tull <atull@kernel.org> Fixes: 435779fe ("clk: fixed-rate: Convert into a module platform driver") Signed-off-by:
-
Nathan Chancellor authored
Clang warns after commit 8985167e ("clk: s2mps11: Fix matching when built as module and DT node contains compatible"): drivers/clk/clk-s2mps11.c:242:34: warning: variable 's2mps11_dt_match' is not needed and will not be emitted [-Wunneeded-internal-declaration] static const struct of_device_id s2mps11_dt_match[] = { ^ 1 warning generated. This warning happens when a variable is used in some construct that doesn't require a reference to that variable to be emitted in the symbol table; in this case, it's MODULE_DEVICE_TABLE, which only needs to hold the data of the variable, not the variable itself. $ nm -S drivers/clk/clk-s2mps11.o | rg s2mps11_dt_match 00000078 000003d4 R __mod_of__s2mps11_dt_match_device_table Normally, with device ID table variables, it means that the variable just needs to be tied to the device declaration at the bottom of the file, like s2mps11_clk_id: $ nm -S drivers/clk/clk-s2mps11.o | rg s2mps11_clk_id 00000000 00000078 R __mod_platform__s2mps11_clk_id_device_table 00000000 00000078 r s2mps11_clk_id However, because the comment above this deliberately doesn't want this variable added to .of_match_table, we need to mark s2mps11_dt_match as __used to silence this warning. This makes it clear to Clang that the variable is used for something, even if a reference to it isn't being emitted. Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Fixes: 8985167e ("clk: s2mps11: Fix matching when built as module and DT node contains compatible") Signed-off-by:
-
Stephen Boyd authored
Add a module license to match the license at the top of this file and silence a build warning. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
-
Stephen Boyd authored
Merge tag 'v4.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Fixes for static checker warning and a wrong shift value for the mmc on rk3328, as well as setting a hdmi-id on rk3066 for a later driver for the hdmi encoder on it and some adapted rk3288 pll rates to support more and better hdmi rates. * tag 'v4.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call clk: rockchip: use the newly added clock-id for hdmi on RK3066 clk: rockchip: add clock-id for HCLK_HDMI on rk3066 clk: rockchip: fix wrong mmc sample phase shift for rk3328 clk: rockchip: improve rk3288 pll rates for better hdmi output
-
- 17 Oct, 2018 20 commits
-
-
Sricharan R authored
When the Hfplls are reprogrammed during the rate change, the primary muxes which are sourced from the same hfpll for higher frequencies, needs to be switched to the 'safe secondary mux' as the parent for that small window. This is done by registering a clk notifier for the muxes and switching to the safe parent in the PRE_RATE_CHANGE notifier and back to the original parent in the POST_RATE_CHANGE notifier. Signed-off-by:
Sricharan R <sricharan@codeaurora.org> Tested-by:
Craig Tatlor <ctatlor97@gmail.com> Signed-off-by:
-
Stephen Boyd authored
The Krait clock controller controls the krait CPU and the L2 clocks consisting a primary mux and secondary mux. Add document for that. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
-
Stephen Boyd authored
The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Cc: <devicetree@vger.kernel.org> Signed-off-by:
-
Stephen Boyd authored
The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. Documenting the bindings here. Reviewed-by:
-
Stephen Boyd authored
The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. For CPUfreq purposes probe these devices and expose a mux clock that chooses between PXO and PLL8. Cc: <devicetree@vger.kernel.org> Signed-off-by:
-
Stephen Boyd authored
The Krait clocks are made up of a series of muxes and a divider that choose between a fixed rate clock and dedicated HFPLLs for each CPU. Instead of using mmio accesses to remux parents, the Krait implementation exposes the remux control via cp15 registers. Support these clocks. Signed-off-by:
-
Stephen Boyd authored
Describe the HFPLLs present on IPQ806X devices. Signed-off-by:
-
Stephen Boyd authored
Describe the HFPLLs present on MSM8960 and APQ8064 devices. Acked-by: Rob Herring <robh@kernel.org> (bindings) Signed-off-by:
-
Stephen Boyd authored
Adds bindings document for qcom,hfpll instantiated within the Krait processor subsystem as separate register region. Reviewed-by:
-
Stephen Boyd authored
On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Cc: <devicetree@vger.kernel.org> Signed-off-by:
-
Stephen Boyd authored
HFPLLs are the main frequency source for Krait CPU clocks. Add support for changing the rate of these PLLs. Signed-off-by:
-
Stephen Boyd authored
Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window' register to do what you want. The l2cpselr register is not banked per-cpu so we must lock around accesses to it to prevent other CPUs from re-pointing l2cpdr underneath us. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
-
Anson Huang authored
i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
-
Anson Huang authored
i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into clock tree for clock management. Signed-off-by:
-
Anson Huang authored
i.MX6SLL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by:
-
Anson Huang authored
i.MX6SX has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by:
-
Anson Huang authored
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by:
-
Alexandre Belloni authored
Move all the DT backward compatibility code to its own file so it can be deleted later. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
-
Alexandre Belloni authored
Add a driver for the PMC clocks of the at91sam9rl SoC. Signed-off-by:
-
Alexandre Belloni authored
Add a driver for the PMC clocks of the at91sam9x5 SoCs Signed-off-by:
-
