- 09 Jun, 2019 3 commits
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Weihang Li authored
This patch fixes some coding style issues reported by some static code analysis tools and code review, such as modify some comments, rename some variables, log some errors in detail, and fixes some alignment errors. BTW, these cleanups do not change the logic of code. Signed-off-by:
Weihang Li <liweihang@hisilicon.com> Signed-off-by:
Peng Li <lipeng321@huawei.com> Signed-off-by:
Yonglong Liu <liuyonglong@huawei.com> Signed-off-by:
HuiSong Li <lihuisong@huawei.com> Signed-off-by:
Jian Shen <shenjian15@huawei.com> Signed-off-by:
Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Weihang Li authored
We trigger PF reset when a RAS error of NIC named over_8bd_nfe_err occurred before. But it is possible that a VF causes that error, it's reasonable to trigger VF reset instead of PF reset in this case. This patch add detection of vf_id if a over_8bd_nfe_err occurs, if vf_id is 0, we trigger PF reset. Otherwise, we will trigger VF reset on the VF with error. Signed-off-by:
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Xiaofei Tan authored
This patch logs detail error info of ROCEE ECC and AXI errors for debug purpose, and remove unnecessary reset for ROCEE overflow errors. Signed-off-by:
Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by:
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- 03 Jun, 2019 4 commits
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Weihang Li authored
All RAS and MSI-X should be enabled just in the final stage of HNS3 initialization. It means that they should be enabled in hclge_init_xxx_client_instance instead of hclge_ae_dev(). Especially MSI-X, if it is enabled before opening vector0 IRQ, there are some chances that a MSI-X error will cause failure on initialization of NIC client instane. So this patch delays enabling of HW errors. Otherwise, we also separate enabling of ROCE RAS from NIC, because it's not reasonable to enable ROCE RAS if we even don't have a ROCE driver. Signed-off-by:
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Weihang Li authored
There are four commands being used to query and clear RAS and MSI-X interrupts status. They should be contained in array of special opcodes because these commands have several descriptors, and we need to judge return value in the first descriptor rather than the last one as other opcodes. In addition, we shouldn't set the NEXT_FLAG of first descriptor. This patch fixes above issues. Signed-off-by:
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Weihang Li authored
We shouldn't set HNAE3_NONE_RESET bit of the variable that represents a reset request during handling of MSI-X errors, or may cause issue when trigger reset. Signed-off-by:
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Huazhong Tan authored
Since core reset is similar to the global reset, so this patch removes it and uses global reset to replace it. Signed-off-by:
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- 26 Apr, 2019 1 commit
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Weihang Li authored
It's meaningless to trigger reset when failed to send command to IMP, because the failure is usually caused by no authority, illegal command and so on. When that happened, we just need to return the status code for further debugging. Signed-off-by:
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- 20 Apr, 2019 1 commit
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Weihang Li authored
MAC tnl interruptions are different from other type of RAS and MSI-X errors, because some bits, such as OVF/LR/RF will occur during link up and down. The drivers should clear status of all MAC tnl interruption bits but shouldn't print any message that would mislead the users. In case that link down and re-up in a short time because of some reasons, we record when they occurred, and users can query them by debugfs. Signed-off-by:
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- 14 Apr, 2019 1 commit
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Weihang Li authored
According to hardware description, reset level that should be triggered are not consistent in a module. For example, in SSU common errors, the first two bits has no need to do reset, but the other bits need global reset. This patch sets separate reset level for all RAS and MSI-X interrupts by adding a reset_lvel field in struct hclge_hw_error, and fixes some incorrect reset level. Signed-off-by:
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- 10 Mar, 2019 1 commit
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Shiju Jose authored
The commit bfcb79fc ("PCI/ERR: Run error recovery callbacks for all affected devices") affected the non-fatal error recovery logic for the HNS and RDMA devices. This is because each HNS PF under PCIe bus receive callbacks from the AER driver when an error is reported for one of the PF. This causes unwanted PF resets because the HNS decides which PF to reset based on the reset type set. The HNS error handling code sets the reset type based on the hw error type detected. This patch provides fix for the above issue for the recovery of the hw errors in the HNS and RDMA devices. This patch needs backporting to the kernel v5.0+ Fixes: 332fbf57 ("net: hns3: add handling of hw ras errors using new set of commands") Reported-by:
Shiju Jose <shiju.jose@huawei.com> Signed-off-by:
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- 25 Feb, 2019 1 commit
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Shiju Jose authored
Presently the hns reset_type for the roce errors is set in the hclge_log_and_clear_rocee_ras_error function. This function is also called to detect and clear roce errors while enabling the rdma error interrupts. However there is no hns reset requested for this case. This can cause issue of wrong reset_type used with subsequent hns reset as the reset_type set in the above case was not cleared. This patch moves setting of hns reset_type for the roce errors from hclge_log_and_clear_rocee_ras_error function to hclge_handle_rocee_ras_error. Fixes: 630ba007 ("net: hns3: add handling of RDMA RAS errors") Reported-by:
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- 22 Feb, 2019 4 commits
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Weihang Li authored
This patch modify print message of 6th bit of ppp mpf abnormal errors, there is a extra letter e in it. Signed-off-by:
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Weihang Li authored
These bits are enabled now and have been test. Signed-off-by:
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Weihang Li authored
The 3rd and 4th of PPU(RCB) PF Abnormal is RAS errors instead of MSI-X like other bits. This patch adds process of handling and logging this two bits. Otherwise, this patch modifies print message of 28th and 29th bit of PPU MPF Abnormal errors, which keep same with other errors now. Fixes: f69b10b3 ("net: hns3: handle hw errors of PPU(RCB)") Signed-off-by:
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Weihang Li authored
This patch add information of specific bit in log to be consistent with other type of errors, so that we can know which memory of ssu has occurred a ecc ras errors. Signed-off-by:
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- 10 Dec, 2018 1 commit
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Colin Ian King authored
There is a spelling mistake in a msg string, fix this. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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- 07 Dec, 2018 14 commits
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Shiju Jose authored
This patch handles the RDMA RAS errors. 1. Enable RAS interrupt, print error detail info and clear error status. 2. Do CORE reset to recovery when these non-fatal errors happened. Signed-off-by:
Salil Mehta <salil.mehta@huawei.com> Signed-off-by:
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Shiju Jose authored
This patch enables and handles hw errors of the Storage Switch Unit(SSU). Signed-off-by:
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Shiju Jose authored
This patch enables and handles hw RAS and MSIx errors of PPU(RCB). Signed-off-by:
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Shiju Jose authored
This patch handles PF hw errors of PPP(Programmable Packet Processor). Signed-off-by:
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Shiju Jose authored
This patch adds enable and handling of hw errors of the MAC block. Signed-off-by:
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Salil Mehta authored
This patch adds handling for HNS3 hardware errors(non-standard) which are reported through MSIX interrupts and not through PCIe AER channel. These MSIX reported hardware errors are handled using common misc. interrupt handler. Hardware error related registers cannot be cleared in context to the interrupt received as they require *heavy* access to hardware using IMP(Integrated Mangement Processor) commands. Hence, we defer the clearing of such error events till later time. Since, we have defered exact identification of errors we will have to defer the level of receovery/reset which might be required. Hence, a new reset type UNKNOWN reset has been introduced which effectively defers the assertion of the reset till we get hold of kind of errors at later time. Signed-off-by:
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Shiju Jose authored
This patch deletes logging 1 bit errors for the following reasons. 1. AER does not notify 1 bit errors to the device drivers. However AER reports 1 bit errors to the userspace through the trace_aer_event for logging in the rasdaemon. 2. Firmware clears the status of 1 bit errors in the hw registers. Signed-off-by:
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Shiju Jose authored
1. This patch adds handling of hw ras errors using new set of common commands. 2. Updated the error message tables to match the register's name and error status returned by the commands. Signed-off-by:
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Shiju Jose authored
1. This patch adds minor loop optimization in the hclge_hw_error_set_state function. 2. Adds logging module's name if it fails to configure the error interrupts. Signed-off-by:
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Shiju Jose authored
This patch renames process_hw_error function to handle_hw_ras_error function to match the purpose of the function. This is because hw errors reported through ras and msix interrupts will be handled separately. Signed-off-by:
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Shiju Jose authored
This patch deletes unnecessary setting of the descriptor data to 0 for disabling error interrupts because it is already done by the hclge_cmd_setup_basic_desc function. Signed-off-by:
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Shiju Jose authored
This patch adds calling hclge_hw_error_set_state function to re-enable the error interrupts those will be disabled on the hw reset. Signed-off-by:
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Shiju Jose authored
This patch - renames the enable error interrupt functions. The reason is that these functions are used for both enable and disable error interrupts. - removes redundant logs from the enable error interrupt functions. Signed-off-by:
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Shiju Jose authored
1.The command interface for queryng and clearing hw errors is changed, which requires the new process error functions to be added. This patch removes all the current process error functions and associated definitions. The new functions to handle ras errors would be added in this patch set. 2. Fixed order issue of the hw_blk table. Signed-off-by:
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- 07 Nov, 2018 1 commit
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YueHaibing authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c: In function 'hclge_log_and_clear_ppp_error': drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c:821:24: warning: variable 'reset_level' set but not used [-Wunused-but-set-variable] enum hnae3_reset_type reset_level = HNAE3_NONE_RESET; It never used since introduction in commit 01865a50 ("net: hns3: Add enable and process hw errors of TM scheduler") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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- 31 Oct, 2018 1 commit
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Colin Ian King authored
Trivial fix to spelling mistake in dev_err message Signed-off-by:
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- 24 Oct, 2018 1 commit
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Shiju Jose authored
This patch fixes the smatch warning, drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c:700 hclge_log_and_clear_ppp_error() error: uninitialized symbol 'hw_err_lst3' Link: https://lkml.org/lkml/2018/10/23/430 Fixes: da2d072a ("net: hns3: Add enable and process hw errors from PPP") Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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- 23 Oct, 2018 6 commits
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Shiju Jose authored
This patch enables and process hw errors of TM scheduler and QCN(Quantized Congestion Control). Signed-off-by:
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Shiju Jose authored
This patch enables and process hw errors from the PPP(Programmable Packet Process) block. Signed-off-by:
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Shiju Jose authored
This patch adds enable and processing of hw errors from IGU(Ingress Unit), EGU(Egress Unit) and NCSI(Network Controller Sideband Interface). Signed-off-by:
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Shiju Jose authored
This patch adds enable and processing of ecc errors from common HNS blocks, CMDQ(Command Queue), IMP(Integrated Management Processor) and TQP(Task Queue Pair). Signed-off-by:
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Shiju Jose authored
This patch adds functions to enable and disable hw errors. Signed-off-by:
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Shiju Jose authored
Set of hw errors occurred in the HNS3 are reported to the hns3 driver through PCIe AER and RAS.The error info will be processed and appropriately recovered. This patch adds error_detected callback and error processing. Signed-off-by:
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