- 22 Jan, 2024 40 commits
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Hawking Zhang authored
amdgpu_reg_state_sysfs_fini could be invoked at the time when asic_func is even not initialized, i.e., amdgpu_discovery_init fails for some reason. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yang Wang authored
skip call ras_late_init callback if ras block is not supported. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Lijo Lazar authored
Ony if vram vendor info is available, show in sysfs. Signed-off-by:
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Lijo Lazar authored
For GFX 9.4.3 APUs, the current method of fetching vram vendor information is not reliable. Avoid fetching the information. Signed-off-by:
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Kenneth Feng authored
update the power cap setting for smu_v13.0.0/smu_v13.0.7 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2356Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
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Ma Jun authored
The power source flag should be updated when [1] System receives an interrupt indicating that the power source has changed. [2] System resumes from suspend or runtime suspend Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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Aric Cyr authored
- FW Release 0.0.201.0 - Fix resizing video window for dcn321 - Fix timing bandwidth calculation for HDMI - Fix null-deref in dml2 assigned pipe search - Add GART memory support for dmcub - Add power_state and pme_pending flag - Add usb4_bw_alloc_support flag - Revert "Rework DC Z10 restore Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- Add debug flag for Replay IPS visual confirm - Remove unused debug flags that should not be controlled inside Replay FSM Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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ChunTao Tso authored
[Why] Because ABM will wait VStart to start getting histogram data, it will cause we can't enter IPS while full screnn video playing. [How] Modify the panel refresh rate to the maximun multiple of current refresh rate. Reviewed-by:
Dennis Chan <dennis.chan@amd.com> Acked-by:
ChunTao Tso <chuntao.tso@amd.com> Tested-by:
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Wenjing Liu authored
[why] It has been found a regression caused by enabling this feature during ODM to MPC combine switch when user is resizing video window. The transition is only needed when the feature is enabled. During the transition driver will temporary switch to use max dppclk level through SMU set hard min interface. The interface times out and fail to configure the max dpp clock level, which caused system issue as the desired clock can't be set. We will continue investigating the issue and root cause the issue where max dppclk level can't be reached. But for now we have to disable this feature as this feature will cause us to hit this problem in common use cases during video playback unfortunately. The issue is dcn321 specific so it won't impact other dcn revisions. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Fudongwang authored
[Why] In dump file, GART memory can be accessed while frame buffer cannot. [How] Add GART memory support for dmcub. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Fudongwang <fudong.wang@amd.com> Tested-by:
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Charlene Liu authored
This reverts commit e6f82bd4. It caused intermittent hangs when enabling IPS on static screen. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Tested-by:
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Muhammad Ahmed authored
[what] Adding power_state to dc.h and pme_pending flag to clk_mgr_internal.h Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Roman Li authored
[Why] With IPS enabled a system hangs once PSR is active. PSR active triggers transition to IPS2 state. While in IPS2 an access to dcn registers results in hard hang. Existing check doesn't cover for PSR sequence. [How] Safeguard register access by disabling idle optimization in atomic commit and crtc scanout. It will be re-enabled on next vblank. Reviewed-by:
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Allen Pan authored
[Why] NULL-deref regression after: "drm/amd/display: Fix dml2 assigned pipe search" [How] Add verification for potential NULLs Fixes: d451b534 ("drm/amd/display: Fix dml2 assigned pipe search") Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
Allen Pan <allen.pan@amd.com> Tested-by:
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Peichen Huang authored
[Why] dc should have a flag for DM to enable usb4_bw_alloc in dptx [How] - Add usb4_bw_alloc_support flag in dc_config Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Acked-by:
Peichen Huang <peichen.huang@amd.com> Tested-by:
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Aric Cyr authored
Acked-by:
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Melissa Wen authored
Logging DCN3 MPC state was following DCN1 implementation that doesn't consider new DCN3 MPC color blocks. Create new elements according to DCN3 MPC color caps and a new DCN3-specific function for reading MPC data. v3: - remove gamut remap reg reading in favor of fixed31_32 matrix data Signed-off-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Leo (Hanghong) Ma authored
[Why && How] The current bandwidth calculation for timing doesn't account for certain HDMI modes overhead which leads to DSC can't be enabled. Add support to calculate the actual bandwidth for these HDMI modes. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by:
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Melissa Wen authored
We want to be able to read the MPC's gamut remap matrix similar to what we do with .dpp_get_gamut_remap functions. On the other hand, we don't need a hook here because only DCN3+ has the MPC gamut remap block, being absent in previous families. Signed-off-by:
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Melissa Wen authored
DCN3 DPP color state was uncollected and some state elements from DCN1 doesn't fit DCN3. Create new elements according to DCN3 color caps and fill them up for DTN log output. rfc-v2: - fix reading of gamcor and blnd gamma states - remove gamut remap register in favor of gamut remap matrix reading Signed-off-by:
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Melissa Wen authored
Instead of read gamut remap data from hw values, convert HW register values (S2D13) into a fixed-point 31.32 matrix for color state log. Change DCN10 log to print data in the format of the gamut remap matrix. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Harry Wentland authored
We want to be able to read the DPP's gamut remap matrix. v2: - code-style and doc comments clean-up (Melissa) Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Melissa Wen authored
Prepare to hook up color state log according to the DCN version. v3: - put functions in single line (Siqueira) Signed-off-by:
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Srinivasan Shanmugam authored
drm/amd/display: Fix uninitialized variable usage in core_link_ 'read_dpcd() & write_dpcd()' functions The 'status' variable in 'core_link_read_dpcd()' & 'core_link_write_dpcd()' was uninitialized. Thus, initializing 'status' variable to 'DC_ERROR_UNEXPECTED' by default. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dpcd.c:226 core_link_read_dpcd() error: uninitialized symbol 'status'. drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dpcd.c:248 core_link_write_dpcd() error: uninitialized symbol 'status'. Cc: stable@vger.kernel.org Cc: Jerry Zuo <jerry.zuo@amd.com> Cc: Jun Lei <Jun.Lei@amd.com> Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Tao Zhou authored
Support page retirement handling in debug mode. v2: revert smu_v13_0_6_get_ecc_info directly. Signed-off-by:
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Tao Zhou authored
This reverts commit 6fe08f56. We use debug mode flag instead of this interface. Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_replay.c:262: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Set REPLAY power optimization flags and coasting vtotal. drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_replay.c:284: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * send Replay general cmd to DMUB. Fixes: e379787c ("drm/amd/display: Add some functions for Panel Replay") Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:645 amdgpu_gfx_enable_kcq() warn: inconsistent indenting Cc: Le Ma <Le.Ma@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
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Yang Wang authored
update smu v13.0.6 message to allow guest driver set gfx clock. Signed-off-by:
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YiPeng Chai authored
Support retiring multiple MCA error address pages in one in-band query for umc v12_0. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
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YiPeng Chai authored
Add interface to check mca umc status. Signed-off-by:
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YiPeng Chai authored
Use asynchronous polling to handle umc_v12_0 poisoning. v2: 1. Change function name. 2. Change the debugging information content. Signed-off-by:
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Stanley.Yang authored
The high three bits of ras features mask indicate socket id, it should skip to check high three bits of ras features mask before disable all ras features. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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YiPeng Chai authored
Preparing for asynchronous processing of umc page retirement. Signed-off-by:
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YiPeng Chai authored
Add log info for umc_v12_0. v2: Delete redundant logs. Signed-off-by:
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Samasth Norway Ananda authored
voltage_parameters is a point to a struct of type SET_VOLTAGE_PARAMETERS_V1_3. Passing just voltage_parameters would not print the right size of the struct variable. So we need to pass *voltage_parameters to sizeof(). Fixes: 4630d503 ("drm/amdgpu: check PS, WS index") Signed-off-by:
Samasth Norway Ananda <samasth.norway.ananda@oracle.com> Signed-off-by:
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Arunpravin Paneer Selvam authored
- Enable the seq64 mapping sequence. - Fix wflinfo va conflict and other bugs. v1: - The seq64 area needs to be included in the AMDGPU_VA_RESERVED_SIZE otherwise the areas will conflict with user space allocations (Alex) - It needs to be mapped read only in the user VM (Alex) v2: - Instead of just one define for TOP/BOTTOM reserved space separate them into two (Christian) - Fix the CPU and VA calculations and while at it also cleanup error handling and kerneldoc (Christian) Signed-off-by:Christian König <christian.koenig@amd.com> Signed-off-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by:
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Nikita Zhandarovich authored
'leakage_table' will always be successfully initialized as a pointer to '&rdev->pm.dpm.dyn_state.cac_leakage_table'. Remove unnecessary check if only to silence static checkers. Found by Linux Verification Center (linuxtesting.org) with static analysis tool Svace. Fixes: 69e0b57a ("drm/radeon/kms: add dpm support for cayman (v5)") Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Nikita Zhandarovich authored
Inside the if block with (running == 0), the checks for 'running' possibly being non-zero are redundant. Remove them altogether. This change is similar to the one authored by Heinrich Schuchardt <xypron.glpk@gmx.de> in commit ddbbd3be ("drm/radeon: remove dead code, si_mc_load_microcode (v2)") Found by Linux Verification Center (linuxtesting.org) with static analysis tool Svace. Fixes: 0af62b01 ("drm/radeon/kms: add ucode loader for NI") Signed-off-by:
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