- 26 Sep, 2017 40 commits
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Harry Wentland authored
Still one more in dc_validate_global Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Powering down the clock source during unref is unsafe as we might want to unref during atomic_check Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Andrew Jiang authored
Since there was no return statement in the fail block immediately preceding the context_alloc_fail block, any failure within the function caused a context alloc failed error message to be printed. Since the context_alloc_fail block is only used once, move it to where the goto is directly and accompany it with a return statement. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Tony Cheng authored
bug: default is mapped to no dithering. default to spatial dithering based on color depth Signed-off-by:
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Harry Wentland authored
This should only happen on full update. If this ever happens on regular pageflips it needs to be debugged. Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Wenjing Liu authored
Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Hersen Wu authored
RV1 support only USB-C active DP-2-HDMI dongle. HPD short pulse is generated only for DP signal. When processing HPD short pulse, it must be DP active dongle. No need for I2C-Over-AUX detection. v2: Add description Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Shirish S authored
For MPO to work with per surface rendering and flipping, the previous logic of restricting plane[1] only as underlay needs to be removed. validate_surface_sets() now checks only the width and height bounds in case of underlay rather than checking format. Without this patch one cannot set underlay only. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Hersen Wu authored
TODO: Current change only work for sucessive last fused pipe, like p3, or p3,p2. It does not work for fused p1,p2. Signed-off-by:
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Wenjing Liu authored
[Description] We originally use TPS4 phy test pattern for test pattern 7. On RV we switched to a new method to use CP2520. CP2520 should produce the same result. However in reality, it fails DP PHY automation test. We use the original method instead. Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Yongqiang Sun authored
In case of vstartup happens before vsync, set vertical line start to 0. Signed-off-by:
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Logatharshan Thothiralingam authored
Signed-off-by:
Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com> Reviewed-by:
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Harry Wentland authored
No more need since Andrey's change to use drm_crtc's version Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
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Tony Cheng authored
Signed-off-by:
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Harry Wentland authored
In a lot of case we fail validation of timings for legitimate reasons. No need to print an error. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
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Roman Li authored
Fixing screen flickering when FBC enabled on Stoney Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Eric Yang authored
On boot, hubp 0 is powergated during enable accel mode, so we time out when we try to blank in undo wa. Fix: Check power gate status before set blank Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
dis_clk is single instance across pipes. Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Mikita Lipski authored
Fix to allow DVI displays to share the same clock source Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Rename dc_resource methods from validate_ctx to state Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Jerry Zuo authored
Rename all the dc validate_context to dc_state and dc current_context to current_state. Signed-off-by:
Jerry Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Yue Hin Lau authored
Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
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Hersen Wu authored
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Yue Hin Lau authored
Signed-off-by:
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Jerry Zuo authored
The fix is for the scenario: MST+SST chain together, and hook up to the card. Regression: Per stream validate_context build v2 Before dc_add_stream_to_ctx(), need to update/reset stream signal type to SIGNAL_TYPE_DISPLAY_PORT_MST. Otherwise, downstream device cannot be added to ctx due to the lack of signal type info (SIGNAL_TYPE_NONE). update_stream_signal() needs to be done after stream is created. Signed-off-by:
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