- 22 Sep, 2020 1 commit
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Akhil P Oommen authored
In the case where we have a back-to-back submission that shares the same BO, this BO will be prematurely moved to inactive_list while retiring the first submit. But it will be still part of the second submit which is being processed by the GPU. Now, if the shrinker happens to be triggered at this point, it will result in a premature purging of this BO. To fix this, we need to refcount BO while doing submit and retire. Then, it should be moved to inactive list when this refcount becomes 0. Signed-off-by:
Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@chromium.org>
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- 20 Sep, 2020 3 commits
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Georgi Djakov authored
The dependency on interconnect in the Kconfig was introduced to avoid the case of interconnect=m and driver=y, but the interconnect framework has been converted from tristate to bool now. Remove the dependency as the framework can't be a module anymore. Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Jordan Crouse authored
Commit 604234f3 ("drm/msm: Enable expanded apriv support for a650") was checking the result of adreno_is_a650() before the gpu revision got probed in adreno_gpu_init() so it was always coming across as false. Snoop into the revision ID ahead of time to correctly set the hw_apriv flag so that it can be used by msm_gpu to properly setup global buffers. Fixes: 604234f3 ("drm/msm: Enable expanded apriv support for a650") Reported-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
Jordan Crouse <jcrouse@codeaurora.org> Tested-by:
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Stephen Boyd authored
We shouldn't be waiting for an event here with a timeout of 100ms when we're not in the 'timeout' arm of the if condition. Instead we should be sleeping in the interruptible state (S) until something happens and we need to wakeup. Right now this kthread is running almost all the time because it sleeps for 100ms, wakes up, sees there's nothing to do, and then starts the process all over again. Looking at top it shows up in the D state (uninterruptible) because it uses wait_event_timeout(). FIx this up. Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Kuogee Hsieh <khsieh@codeaurora.org> Reported-by:
Douglas Anderson <dianders@chromium.org> Fixes: 8ede2ecc ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Kuogee Hsieh <khsieh@codeaurora.org> Signed-off-by:
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- 19 Sep, 2020 1 commit
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Rob Clark authored
Signed-off-by:
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- 15 Sep, 2020 19 commits
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Stephen Boyd authored
Make the necessary changes to the DP driver to use the qmp phy from the common phy framework instead of rolling our own in the drm subsystem. This also removes the PLL code and adds proper includes so things build. Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by:
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Abhinav Kumar authored
No need to fix the number of resolutions to one during the video pattern CTS test. The userspace test client will handle both the hotplug as well as picking the right resolution for the test. Changes in v2: rebase on top of latest patchset of dependency Signed-off-by:
Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by:
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Abhinav Kumar authored
Add the debugfs nodes needed for the video pattern compliance tests to MSM DP driver. Changes in v2: rebase on top of latest patchset of dependency Signed-off-by:
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Abhinav Kumar authored
Move the MSM DP debugfs node from /sys/kernel/debug/drm_dp to /sys/kernel/debug/dri/*/ as required for video pattern compliance test suite. Changes in v2: rebase on top of latest patchset of dependency Signed-off-by:
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Abhinav Kumar authored
To prepare the MSM DP driver for running video pattern compliance tests introduce debugfs module for it. Changes in v2: rebase on top of latest patchset of dependency Signed-off-by:
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Abhinav Kumar authored
In the current implementation, there is a very small window for the audio side to safely signal the hdmi_code_shutdown() before the clocks are disabled. Add some synchronization between the DP display and DP audio module to safely disable the clocks to avoid unclocked access from audio side. In addition, audio side can open the sound card even if DP monitor is not connected. Avoid programming hardware registers in this case and bail out early. Changes in v4: - removed some leftover prints Changes in v5: - fix crash when user tries to play audio in suspended state Changes in v6: - rebased on top of latest patchset of dependency Signed-off-by:
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Abhinav Kumar authored
Signal the hotplug disconnect event to the audio side in the event handler so that they are notified earlier and have more time to process the disconnect event. Changes in v2: none Changes in v3: none Changes in v4: rebase on top of latest patchset of dependency Changes in v5: rebase on top of latest patchset of dependency Changes in v6: none Signed-off-by:
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Abhinav Kumar authored
Add the hook_plugged_cb op for the MSM DP driver to signal connect and disconnect events to the hdmi-codec driver which in-turn shall notify the audio subsystem to start a new or teardown an existing session. Changes in v2: none Changes in v3: none Changes in v4: rebase on top of latest patchset of dependency Changes in v5: rebase on top of latest patchset of dependency Changes in v6: none Signed-off-by:
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Abhinav Kumar authored
Introduce audio support for Display Port on MSM chipsets. This change integrates DP audio sub-module with the main Display Port platform driver. In addition, this change leverages hdmi_codec_ops to expose the operations to the audio driver. Changes in v2: fix up a compilation issue on drm-next branch Changes in v3: none Changes in v4: none Changes in v5: none Changes in v6: rebase on top of latest patchset of dependency Signed-off-by:
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Abhinav Kumar authored
Store the dp_display in the platform driver data instead of the dp_display_private. This is required to allow other sub-modules to reuse the platform driver data. Changes in v3: none Changes in v4: none Changes in v5: none Changes in v6: rebase on top of latest patchset of dependency Signed-off-by:
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Kuogee Hsieh authored
add event thread to execute events serially from event queue. Also timeout mode is supported which allow an event be deferred to be executed at later time. Both link and phy compliant tests had been done successfully. Changes in v2: -- Fix potential deadlock by removing redundant connect_mutex -- Check and enable link clock during modeset -- Drop unused code and fix function prototypes. -- set sink power to normal operation state (D0) before DPCD read Changes in v3: -- push idle pattern at main link before timing generator off -- add timeout handles for both connect and disconnect Changes in v4: -- add ST_SUSPEND_PENDING to handles suspend/modeset test operations -- clear dp phy aux interrupt status when ERR_DPPHY_AUX error -- send segment addr during edid read -- clear bpp depth before MISC register write Changes in v5: -- add ST_SUSPENDED to fix crash at resume Changes in v6: -- at msm_dp_display_enable() do not return until resume_done to avoid kms commit timeout Signed-off-by:
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Tanmay Shah authored
Configure HPD registers in DP controller and enable HPD interrupt. Add interrupt to handle HPD connect and disconnect events. Changes in v8: None Signed-off-by:
Tanmay Shah <tanmay@codeaurora.org> Signed-off-by:
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Jeykumar Sankaran authored
Add display port support in DPU by creating hooks for DP encoder enumeration and encoder mode initialization. changes in v2: - rebase on [2] (Sean Paul) - remove unwanted error checks and switch cases (Jordan Crouse) [1] https://lwn.net/Articles/768265/ [2] https://lkml.org/lkml/2018/11/17/87 changes in V3: -- Moved this change as part of the DP driver changes. -- Addressed compilation issues on the latest code base. Changes in v6: -- Fix checkpatch.pl warning Changes in v7: Remove depends-on tag from commit message. Changes in v8: None Changes in v9: None Signed-off-by:
Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by:
Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by:
Vara Reddy <varar@codeaurora.org> Signed-off-by:
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Chandan Uddaraju authored
Add the needed DP PLL specific files to support display port interface on msm targets. The DP driver calls the DP PLL driver registration. The DP driver sets the link and pixel clock sources. Changes in v2: -- Update copyright markings on all relevant files. -- Use DRM_DEBUG_DP for debug msgs. Changes in v4: -- Update the DP link clock provider names Changes in V5: -- Addressed comments from Stephen Boyd, Rob clark. Changes in V6: -- Remove PLL as separate driver and include PLL as DP module -- Remove redundant clock parsing from PLL module and make DP as clock provider -- Map USB3 DPCOM and PHY IO using hardcoded register address and move mapping form parser to PLL module -- Access DP PHY modules from same base address using offsets instead of deriving base address of individual module from device tree. -- Remove dp_pll_10nm_util.c and include its functionality in dp_pll_10nm.c -- Introduce new data structures private to PLL module Changes in v7: -- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig -- Remove set_parent from determin_rate API -- Remove phy_pll_vco_div_clk from parent list -- Remove flag CLK_DIVIDER_ONE_BASED -- Remove redundant cell-index property parsing Changes in v8: -- Unregister hardware clocks during driver cleanup Changes in v9: -- Remove redundant Kconfig option DRM_MSM_DP_10NM_PLL Changes in v10: -- Limit 10nm PLL function scope Signed-off-by:
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Chandan Uddaraju authored
Add the needed displayPort files to enable DP driver on msm target. "dp_display" module is the main module that calls into other sub-modules. "dp_drm" file represents the interface between DRM framework and DP driver. Changes in v12: -- Add support of pm ops in display port driver -- Clear bpp depth bits before writing to MISC register -- Fix edid read Previous Change log: https://lkml.kernel.org/lkml/20200818051137.21478-3-tanmay@codeaurora.org/Signed-off-by:
Guenter Roeck <groeck@chromium.org> Signed-off-by:
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Chandan Uddaraju authored
The constant N value (0x8000) is used by i915 DP driver. Define this value in dp helper header file to use in multiple Display Port drivers. Change i915 driver accordingly. Change in v6: Change commit message Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Jordan Crouse authored
As newer GPU families are added it makes less sense to maintain a "generic" version functions for older families. Move adreno_submit() and get_rptr() into the target specific code for a2xx, a3xx and a4xx. Add a parameter to adreno_flush to pass the target specific WPTR register instead of relying on the generic register. All of this gets rid of the last of the REG_ADRENO offsets so remove all all the register definitions and infrastructure. Signed-off-by:
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Jordan Crouse authored
Support the WHERE_AM_I opcode for the A618, A630 and A640 GPUs if the microcode supports it. The WHERE_AM_I opcode allows the RPTR shadow to be updated in priviliged memory which protects the shadow from being read or written from user submissions. A650 already supports extended APRIV have built in hardware support for to access privilged memory from the CP and can go back to using the hardware RPTR shadow feature. Signed-off-by:
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Jordan Crouse authored
Newer microcode versions have support for the CP_WHERE_AM_I opcode which allows the RPTR shadow memory to be marked as privileged to protect it from corruption. Move the RPTR shadow into its own buffer and protect it it if the current microcode version supports the new feature. We can also re-enable preemption for those targets that support CP_WHERE_AM_I. Start out by preemptively assuming that we can enable preemption and disable it in a5xx_hw_init if the microcode version comes back as too old. Signed-off-by:
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- 12 Sep, 2020 16 commits
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Rob Clark authored
In $debugfs/gem we already show any vma(s) associated with an object. Also show process names if the vma's address space is a per-process address space. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org>
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Jordan Crouse authored
Add support for using per-instance pagetables if all the dependencies are available. Signed-off-by:
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Jordan Crouse authored
Add support for allocating private address space instances. Targets that support per-context pagetables should implement their own function to allocate private address spaces. The default will return a pointer to the global address space. Signed-off-by:
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Jordan Crouse authored
Add support to create a io-pgtable for use by targets that support per-instance pagetables. In order to support per-instance pagetables the GPU SMMU device needs to have the qcom,adreno-smmu compatible string and split pagetables enabled. Signed-off-by:
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Jordan Crouse authored
Use the aperture settings from the IOMMU domain to set up the virtual address range for the GPU. This allows us to transparently deal with IOMMU side features (like split pagetables). Signed-off-by:
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Jordan Crouse authored
Now that we can get the ctx from the submitqueue, the extra arg is redundant. Signed-off-by:
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Jordan Crouse authored
Each submitqueue is attached to a context. Add a pointer to the context to the submitqueue at create time and refcount it so that it stays around through the life of the queue. Co-developed-by:
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Rob Clark authored
This will be populated by adreno-smmu, to provide a way for coordinating enabling/disabling TTBR0 translation. Signed-off-by:
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Rob Clark authored
In a later patch, the drvdata will not directly be 'struct msm_gpu *', so add a helper to reduce the churn. Signed-off-by:
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Rob Clark authored
This interface will be used for drm/msm to coordinate with the qcom_adreno_smmu_impl to enable/disable TTBR0 translation. Once TTBR0 translation is enabled, the GPU's CP (Command Processor) will directly switch TTBR0 pgtables (and do the necessary TLB inv) synchronized to the GPU's operation. But help from the SMMU driver is needed to initially bootstrap TTBR0 translation, which cannot be done from the GPU. Since this is a very special case, a private interface is used to avoid adding highly driver specific things to the public iommu interface. Signed-off-by:
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Rob Clark authored
Currently it doesn't matter, since we free the ctx immediately. But when we start refcnt'ing the ctx, we don't want old dangling list entries to hang around. Signed-off-by:
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Zhenzhong Duan authored
It's allocating an array of a6xx_gpu_state_obj structure rathor than its pointers. This patch fix it. Signed-off-by:
Zhenzhong Duan <zhenzhong.duan@gmail.com> Signed-off-by:
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Luca Weiss authored
The function iommu_domain_alloc returns NULL on platforms without IOMMU such as msm8974. This resulted in PTR_ERR(-ENODEV) being assigned to gpu->aspace so the correct code path wasn't taken. Fixes: ccac7ce3 ("drm/msm: Refactor address space initialization") Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Rob Clark authored
Signed-off-by: -
Jonathan Marek authored
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250. Implementation is based on 10nm driver, but updated based on the downstream 7nm driver. Signed-off-by: -
Jonathan Marek authored
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config is re-used as the config is the same. Signed-off-by:
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