- 24 Apr, 2013 3 commits
-
-
Sachin Kamat authored
Instead of checking if num_encoders is zero, it is being assigned 0. Convert the assignment to a check. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Acked-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
-
Mika Kuoppala authored
commit ae128786 Author: Dave Airlie <airlied@redhat.com> Date: Thu Jan 24 16:12:41 2013 +1000 fbcon: don't lose the console font across generic->chip driver switch uses a pointer in vc->vc_font.data to load font into the new driver. However if the font is actually freed, we need to clear the data so that we don't reload font from dangling pointer. Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=892340Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Cc: stable@vger.kernel.org Signed-off-by:
-
git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Alex writes: A few more updates for 3.10. Nothing too major here. Mostly bug fixes. The big changes are adding golden register init for 7xx and newer asics and some audio cleanups. * 'drm-next-3.10-2' of git://people.freedesktop.org/~agd5f/linux: (32 commits) drm/radeon: disable UVD advanced semaphore mode drm/radeon: fix endian bugs in radeon_atom_get_clock_dividers() (v3) drm/radeon: fix up audio dto programming for DCE2 drm/radeon/evergreen: set SAD registers drm: add drm_edid_to_eld helper extracting SADs from EDID (v2) drm/radeon/si: add support for golden register init drm/radeon/cayman,TN: add support for golden register init (v2) drm/radeon/evergreen: add support for golden register init drm/radeon/7xx: add support for golden register init drm/radeon: add helper function to support golden registers drm/radeon: fix typo in si_select_se_sh() drm/radeon: switch audio handling to use callbacks drm/radeon: clean up audio dto programming drm/radeon: clean up audio supported check drm/radeon: raise UVD clocks on init v3 drm/radeon: raise UVD clocks only on demand drm/radeon: put UVD PLLs in bypass mode drm/radeon: disable audio format interrupts on Evergreen drm/radeon: fix hdmi mode enable on RS600/RS690/RS740 drm/radeon/evergreen: write default channel numbers ...
-
- 23 Apr, 2013 16 commits
-
-
Christian König authored
Not needed and seems to cause some problems. Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Alex Deucher authored
v2: fix copy paste typo. v3: clarify new union member Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
-
Alex Deucher authored
Uses a different register than DCE3 asics. Signed-off-by: -
Rafał Miłecki authored
This allows audio (alsa) driver to read them and have a clue about audio capabilities of connected receiver. This has been verified to be compatible with fglrx behaviour for Onkyo TX-SR605 and Denon 1912. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
-
Rafał Miłecki authored
Some devices (ATI/AMD cards) don't support passing ELD struct to the hardware but just require filling specific registers and then the hardware/firmware does the rest. In such cases we need to read the info from SAD blocks and put them in the correct registers. agd5f: note that the returned pointer needs to be kfreed as per Christian's suggestion. v2: fix warning Signed-off-by:
-
Alex Deucher authored
Signed-off-by: -
Alex Deucher authored
v2: add richland support Signed-off-by: -
Alex Deucher authored
Signed-off-by: -
Alex Deucher authored
Signed-off-by: -
Alex Deucher authored
Golden registers are arrays of register settings from the hw team that need to be initialized at asic startup. Signed-off-by: -
Alex Deucher authored
Signed-off-by: -
Alex Deucher authored
Register audio callbacks for asic where we support audio. Cleans up the code and makes it easier to add support for newer asics. Reviewed-by:
-
Alex Deucher authored
Split into DCE2/3 and DCE4/5 variants. Still todo is to calculate the DTO dividers properly. Add proper formula to the comments. Reviewed-by:
-
Alex Deucher authored
Reviewed-by:
-
Christian König authored
v2: not only raise the clocks on VCPU boot, but also on IB test. v3: agd5f: fix r600_uvd_init return value. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=63730Signed-off-by:
-
Christian König authored
That not only saves some power, but also solves problems with older chips where an idle UVD block on higher clocks can cause problems. Signed-off-by:
-
- 22 Apr, 2013 21 commits
-
-
Christian König authored
Just power down the PLL when we get a VCLK or DCLK of zero. Enabling the bypass mode early should also allow us to switch UVD clocks on the fly. Signed-off-by:
-
Alex Deucher authored
The audio format change interrupts are an aid in debugging, but not required for operation. Signed-off-by: -
Alex Deucher authored
These chips were previously skipped since they are pre-R600. Signed-off-by: -
Rafał Miłecki authored
Signed-off-by:
-
Rafał Miłecki authored
Driver fglrx setups audio and ACR packets after basic initialization, which sounds sane, do the same. Signed-off-by:
-
Rafał Miłecki authored
Closed source driver fglrx seems to enable infoframes and audio packets at the end, which makes sense, do the same. Signed-off-by:
-
Rafał Miłecki authored
Signed-off-by:
-
Christian König authored
Signed-off-by:
-
Christian König authored
Message and feedback buffers must be at start of VRAM, not at start of address space. Signed-off-by:
-
Alex Deucher authored
Just disabling the mem requests should be enough, but that doesn't seem to work correctly on efi systems. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=57567 https://bugs.freedesktop.org/show_bug.cgi?id=43655 https://bugzilla.kernel.org/show_bug.cgi?id=56441 v2: blank displays first, then disable. Signed-off-by:
-
Alex Deucher authored
Just disabling the mem requests should be enough, but that doesn't seem to work correctly on efi systems. v2: blank displays first, then disable. Signed-off-by: -
Alex Deucher authored
Need to wait for the new addresses to take affect before re-enabling the MC. Signed-off-by: -
Alex Deucher authored
Need to wait for the new addresses to take affect before re-enabling the MC. Signed-off-by: -
Alex Deucher authored
Properly wait for the next vblank region. The previous code didn't always wait long enough depending on the timing. Signed-off-by: -
Alex Deucher authored
Properly wait for the next vblank region. The previous code didn't always wait long enough depending on the timing. Signed-off-by: -
Alex Deucher authored
Properly wait for the next vblank region. The previous code didn't always wait long enough depending on the timing. Signed-off-by: -
git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/tegra: Changes for v3.10-rc1 The bulk of this pull-request is the host1x series that has been in the works for a few months. The current implementation looks good and has been tested by several independent parties. So far no issues have been found. To be on the safe side, the new Tegra-specific DRM IOCTLs depend on staging in order to give some amount of flexibility to change them just in case. The plan is to remove that dependency once more userspace exists to verify the adequacy of the IOCTLs. Currently only the 2D engine is supported, but patches are in the works to enable 3D support on top of this framework as well. Various bits of open-source userspace exist to test the 2D and 3D support[0]. This is still a bit immature but it allows to verify that the kernel interfaces work properly. To round things off there are two smaller cleanup patches, one of them adding a new pixel format and the other removing a redundent Kconfig dependency. [0]: https://github.com/grate-driver * tag 'drm/tegra/for-3.10' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: don't depend on OF drm/tegra: Support the XBGR8888 pixelformat drm/tegra: Add gr2d device gpu: host1x: drm: Add memory manager and fb gpu: host1x: Remove second host1x driver gpu: host1x: drm: Rename host1x to host1x_drm drm/tegra: Move drm to live under host1x gpu: host1x: Add debug support gpu: host1x: Add channel support gpu: host1x: Add syncpoint wait and interrupts gpu: host1x: Add host1x driver
-
Stephen Warren authored
ARCH_TEGRA always enabled OF, so there's no need for any driver to depend on it. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Thierry Reding <thierry.reding@avionic-design.de>
-
Thierry Reding authored
While at it, also include the RGB565 pixelformat in the list of formats supported by overlays. Signed-off-by:
Erik Faye-Lund <kusmabite@gmail.com>
-
Terje Bergstrom authored
Add client driver for 2D device, and IOCTLs to pass work to host1x channel for 2D. Also adds functions that can be called to access sync points from DRM. Signed-off-by:
Arto Merilainen <amerilainen@nvidia.com> Signed-off-by:
Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by:
-
Arto Merilainen authored
This patch introduces a memory manager for tegra drm and moves existing parts to use it. As cma framebuffer helpers can no more be used, this patch adds also a separate framebuffer driver for tegra. Signed-off-by:
-
