The i.MX8M Nano has several SAI nodes available to it.
Enable them.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The driver exists for the Enhanced Asynchronous Sample Rate Converter
(EASRC) Controller, but there isn't a device tree entry for it.

On the vendor kernel, they put this on a spba-bus for SDMA support.

Add the node for the spba-bus with the easrc node inside.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

As the boot order in the kernel continues to change, sometimes it may
happen that the eSDHC controller mmc@2150000 (the one for eMMC) gets
probed before the one at mmc@2140000 (for external SD cards). The effect
is that the eMMC controller gets the /dev/mmcblk0 name, and the SD card
gets /dev/mmcblk1.

Since the introduction of this SoC, that has never happened in practice,
even though it was never guaranteed in theory. Setting
"root=/dev/mmcblk0p2" in /proc/cmdline has always caused the kernel to
use the second partition from the SD card as the rootfs.

The NXP development boards are typically shipped with either
- LSDK, which uses "root=UUID=", or
- OpenIL, which uses "root=/dev/mmcblkNp2"

So for OpenIL, let's preserve that old behavior by adding some aliases
which create naming consistency (for LSDK it doesn't matter):
- the SD card controller uses /dev/mmcblk0
- the eMMC controller uses /dev/mmcblk1

For the Kontron SL28 boards, Michael Walle says that they are shipped
with "root=UUID=" already, so the probing order doesn't matter, but it
is more natural to him for /dev/mmcblk0 to be the eMMC, so let's do it
the other way around there.

The aliases are parsed by mmc_alloc_host() in drivers/mmc/core/host.c.

Cc: Ashish Kumar <Ashish.Kumar@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Cc: Michael Walle <michael@walle.cc>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Update the calibration table to make the temperature more accurate.
Three platforms have been updated: ls1012a, ls1043a and ls1046a.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The upstream port, doesn't really follow the vendor partitioning. The
bootloader partition has one U-Boot FIT image containing all needed
bits and pieces. Even today the bootloader is already larger than the
current "bootloader" partition. Thus, fold all the partitions into one
and keep the environment one. The latter is still valid.
We keep the failsafe partitions because the first half of the SPI flash
is preinstalled by the vendor and immutable.

Fixes: 815364d0 ("arm64: dts: freescale: add Kontron sl28 support")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add the optee node which can either be enabled by a specific board or by
the bootloader.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

On the LS1028A the FlexSPI clock is connected to the first HWA output,
see Figure 7 "Clock subsystem block diagram".

Fixes: c77fae5b ("arm64: dts: ls1028a: Add FlexSPI support")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

On the LS1028A the ENETC reference clock is connected to 4th HWA output,
see Figure 7 "Clock subsystem block diagram".

The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read
the clock speed of the clock given in the device tree. It is likely that,
on the reference board this wasn't noticed because both clocks have the
same frequency. But this must not be always the case. Fix it.

Fixes: 49401003 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

While running 'make dtbs_install', the following error occurs:

make[3]: *** No rule to make target 'rootfs/freescale/imx8mm-kontron-n801x-s.dts', needed by '__dtbs_install'.

It should be .dtb, not .dts.

Fixes: 8668d8b2 ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards")
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add IR support on i.MX8MN EVK board.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add IR support on i.MX8MM EVK board.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add linux,autosuspend-period property for IR, details please refer to:

commit ff1c9223 ("media: rc: gpio-ir-recv: add QoS support for cpuidle system")
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add CAN device node and pinctrl on i.MX8MP evk board.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

There are two spdif IP on imx8mq, spdif1 is for normal
spdif device, spdif2 is for HDMI ARC interface.

Enable these spdif sound card in this patch.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Configure clock rate for audio plls. audio pll1 is used
as parent clock for clocks that is multiple of 8kHz.
audio pll2 is used as parent clock for clocks that is
multiple of 11kHz.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Annotate the EMDIO1 node and describe the 2 AQR107 PHYs found on the
LX2160ARDB board. Also, add the necessary phy-handles for DPMACs 3 and 4
to their associated PHY.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add PCS MDIO nodes for the internal MDIO buses on the LX2160A, along
with their internal PCS PHYs, which will be used when the DPMAC is
in TYPE_PHY mode.
Also, rename the dpmac@x nodes to ethernet@x in order to be compliant
with the naming convention used by ethernet controllers.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add PCS MDIO nodes for the internal MDIO buses on the LS208x SoCs, along
with their internal PCS PHYs which will be used when the DPMAC object is
in TYPE_PHY mode.
Also, rename the dpmac@x nodes to ethernet@x in order to be compliant
with the naming convention used by ethernet controllers.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Annotate the EMDIO2 node and describe the other 4 10GBASER PHYs found on
the LS2088ARDB board. Also, add phy-handles for DPMACs 5-8 to their
associated PHY.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Annotate the EMDIO1 node and describe the 4 10GBASER PHYs found on the
LS2088ARDB board. Also, add phy-handles for DPMACs 1-4 to their
associated PHY.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add the external MDIO device nodes found in the WRIOP global memory
region. This is needed for management of external PHYs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Annotate the external MDIO2 node and describe the 10GBASER PHY found on
the LS1088ARDB board and add a phy-handle for DPMAC2 to link it.
Also, add the internal PCS MDIO node for the internal MDIO buses found
on the LS1088A SoC along with its internal PCS PHY and link the
corresponding DPMAC to the PCS through the pcs-handle.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found on
the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its
associated PHY.  Also, add the internal PCS MDIO nodes for the internal
MDIO buses found on the LS1088A SoC along with their internal PCS PHY
and link the corresponding DPMAC to the PCS through the pcs-handle.
Also, rename the dpmac@x nodes to ethernet@x in order to be compliant
with the naming convention used by ethernet controllers.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add the external MDIO device nodes found in the WRIOP global memory
region. This is needed for management of external PHYs.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add device tree support for LX2162AQDS board.
LX2162A has same die as of LX2160A with different packaging.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The pinmux subnodes are indented too much.  This patch does nothing
more than remove an extra tab.  There are no functional changes.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The i.MX8M Mini can support SPDIF which is compatible to the
IP used on the i.MX35.  Add the node.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The i.MX8M Mini has supports the MICFIL digital interface.
It's a 16-bit audio signal from a PDM microphone bitstream.
The driver is already in the kernel, but the node is missing.

This patch adds the micfil node.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Different revision of i.MX8MP EVK boards may have different external
pull up registor design, some are enabled while some are NOT, to make
sure the WDOG_B pin works properly, better to enable internal pull up
resistor. Since enabling internal pull up resistor is NOT harmful and
having benefit of flexibility on different board design, just enable
it for all i.MX8MP boards; And schmitt input is NOT necessary for this
WDOG_B output pin, so remove it; Open drain outputs provide more
flexibility to a designer as they can be pulled-up to any voltage found
in the system, so enable it as well.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Different revision of i.MX8MN EVK boards may have different external
pull up registor design, some are enabled while some are NOT, to make
sure the WDOG_B pin works properly, better to enable internal pull up
resistor. Since enabling internal pull up resistor is NOT harmful and
having benefit of flexibility on different board design, just enable
it for all i.MX8MN boards; And schmitt input is NOT necessary for this
WDOG_B output pin, so remove it; Open drain outputs provide more
flexibility to a designer as they can be pulled-up to any voltage found
in the system, so enable it as well.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Different revision of i.MX8MM EVK boards may have different external
pull up registor design, some are enabled while some are NOT, to make
sure the WDOG_B pin works properly, better to enable internal pull up
resistor. Since enabling internal pull up resistor is NOT harmful and
having benefit of flexibility on different board design, just enable
it for all i.MX8MM boards; And schmitt input is NOT necessary for this
WDOG_B output pin, so remove it; Open drain outputs provide more
flexibility to a designer as they can be pulled-up to any voltage found
in the system, so enable it as well.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

imx8mm-beacon-som has a Quad-SPI NOR flash connected to the FlexSPI bus.

This patch enables the FlexSPI bus and configures it to work with the
flash part.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Each cpu core should have a corresponding supply, but only cpu0 does.
This patch adds a supply for each of the secondary cpus.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR.

The matching baseboards have the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232,
RS485, CAN, LVDS or HDMI, RTC and much more.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add PMU node to enable pmu support on imx8mn.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add PMU node to enable pmu support on imx8mp.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

i.MX 8M Plus has four Cortex-A CPUs, not six.  Using higher value is
harmless but adjust it to match real HW.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

i.MX 8M Nano has four Cortex-A CPUs, not six.  Using higher value is
harmless but adjust it to match real HW.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>