- 19 Feb, 2018 40 commits
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Signed-off-by:
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Harry Wentland authored
Our APUs (Carrizo, Stoney, Raven) don't support it. v2: Don't use is_apu as other ASICs might also not support it Signed-off-by:
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Harry Wentland authored
It might be good to understand why validate fails. Signed-off-by:
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Yongqiang Sun authored
Proper sequence should be: disable backlight dp blank disable output edp power off In enable accelatate mode, all the encoder and controller are disabled, so move disable eDP to the function is the easiest way to implement. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Harry Wentland authored
This makes the check for HDMI and dual-link DVI a bit more straightforward. Signed-off-by:
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Harry Wentland authored
Signed-off-by:
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Harry Wentland authored
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Yongqiang Sun authored
Signed-off-by:
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Krunoslav Kovac authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Mikita Lipski authored
Verify that the stream is master - and program only the slave displays Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Roman Li authored
With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Yongqiang Sun authored
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Jerry (Fangzhi) Zuo authored
When topology changed and rehook up MST display to the same DP connector, need to take care of drm_dp_mst_port object. Due to the topology is changed, drm_dp_mst_port and corresponding i2c_algorithm object could be NULL in such situation. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Roman Li authored
After reworking FBC init for dynamic mem alloc old FBC init code in DC became redundant. Removing it. Signed-off-by:
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Roman Li authored
- FBC init reworked to alloc memory based on display mode. - Removed asic-dependencies from dm Signed-off-by:
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Ken Chalmers authored
This allows Maximus emulation to more closely mirror actual silicon execution. * Enable pool->base.display_clock creation on Maximus. * Enable rest of dce110_apply_ctx_to_hw on Maximus. * Remove apply_ctx_to_hw_fpga (no longer necessary with the full dce110_apply_ctx_to_hw enabled). * Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock for Maximus (this was the only fix-up necessary after enabling dce110_apply_ctx_to_hw; everything else works unmodified on Maximus). Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Ken Chalmers authored
Maximus testing now defaults to a 700 MHz emulated dispclk Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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Fengguang Wu authored
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:281:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 620f774f ("drm/amdgpu: separate VMID and PASID handling") CC: Christian König <christian.koenig@amd.com> Signed-off-by:
Fengguang Wu <fengguang.wu@intel.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
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Alex Deucher authored
We only need to flush the HDP here, not invalidate the TLB. Reviewed-by:
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Alex Deucher authored
Separate tlb invalidation and hdp flushing and move the HDP flush to the caller. Reviewed-by:
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. v2: use preferred register on soc15. Reviewed-by:
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by:
Samuel Li <Samuel.Li@amd.com>
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by:
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Alex Deucher authored
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by:
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Alex Deucher authored
Needed to properly flush the HDP cache with the CPU from rather than the GPU. Reviewed-by:
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Andres Rodriguez authored
Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Andres Rodriguez authored
We follow the same approach as gfx8. The only changes are register access macros. Tested on vega10. The execution latency results fall within the expected ranges from the polaris10 data. Reviewed-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
V2: reuse the SMUThermal structure defined in pp_thermal.h Signed-off-by:
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Evan Quan authored
V2: move the SMU7Thermal structure to newly created header file Signed-off-by:
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Evan Quan authored
V2: new header file to hold the common SMU7Thermal structure Signed-off-by:
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Alex Deucher authored
Populate the hwmon temp range as part of thermal controller setup. Signed-off-by:
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Evan Quan authored
Added a new callback for asic specific backends to specify the temperature ranges. Signed-off-by:
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Evan Quan authored
This will be used by powerplay to update the dpm temp range structure used to interface with hwmon. Signed-off-by:
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Evan Quan authored
drm/amd/powerplay: correct PP_TemperatureRange member type since negative values are part of the valid range Signed-off-by:
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