- 16 Apr, 2010 40 commits
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Grazvydas Ignotas authored
wl1251 has WLAN_IRQ pin for generating interrupts to host processor, which is mandatory in SPI mode and optional in SDIO mode (which can use SDIO interrupts instead). However TI recommends using deditated IRQ line for SDIO too. Add support for using dedicated interrupt line with SDIO, but also leave ability to switch to SDIO interrupts in case it's needed. Signed-off-by:
Grazvydas Ignotas <notasas@gmail.com> Reviewed-by:
Bob Copeland <me@bobcopeland.com> Signed-off-by:
John W. Linville <linville@tuxdriver.com>
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Sujith authored
This patch fixes a bunch of endian issues that were exposed by sparse. It's a miracle that the driver worked at all till now. The Lord be praised. Signed-off-by:
Sujith <Sujith.Manoharan@atheros.com> Signed-off-by:
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Sujith authored
If a WMI command has timed out for some reason, a late WMI response would end up updating the response region of a new WMI request that has been issued in the meantime. Fix this race condition by dropping a WMI response if a new WMI command has been issued. Signed-off-by:
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Sujith authored
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Sujith authored
There is no point in trying to set the LED pin when the module is being unloaded. The target would be reset anyway. Signed-off-by:
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Sujith authored
This patch adds macros at certain places which could be optimized for multiple register writes. The performance of ath9k_htc improves considerably, especially reducing the latency involved in a scan run. Signed-off-by:
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Sujith authored
Programming the opmode in the HW can be done before the assoc_id and STA_ID registers are setup. This helps ath9k_htc when multiple register writes are used. Signed-off-by:
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Sujith authored
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Sujith authored
This patch adds support for writing multiple registers in a single USB command. Specific calls from the HW code that performs multiple register writes would be modified to make use of this in subsequent patches. Signed-off-by:
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Sujith authored
This is required to implement delayed/buffered register writes in ath9k_htc. Signed-off-by:
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Sujith authored
This patch cleans up beacon configuration, removing a redundant interface type check and updating beacon interval in the correct place. Signed-off-by:
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Samuel Ortiz authored
Add -D__CHECK_ENDIAN__ to driver ccflags so that sparse will always check endianness by default. Signed-off-by:
Samuel Ortiz <sameo@linux.intel.com> Signed-off-by:
Zhu Yi <yi.zhu@intel.com> Signed-off-by:
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Samuel Ortiz authored
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Benoit Papillault authored
According to tests, both TSF lower and upper registers kept counting, so the higher part could have been updated after the lower part has been read, as shown in the following log where the upper part is read first and the lower part next. tsf = {00000003-fffffffd} tsf = {00000003-00000001} tsf = {00000004-0000000b} This patch corrects this by checking that the upper part has not been changed while the lower part was read. It has been tested in an IBSS network where artifical IBSS merges have been done in order to trigger hundreds of rollover for the TSF lower part. It follows the logic mentionned by Derek, with only 2 register reads needed at each additional steps instead of 3 (the minimum number of register reads is still 3). Signed-off-by:Benoit Papillault <benoit.papillault@free.fr> Signed-off-by:
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Luis R. Rodriguez authored
The first AR9003 hardware family device supported is the AR9300, which has the vendor:device id 168c:0030 Signed-off-by:
Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by:
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Vasanthakumar Thiagarajan authored
Signed-off-by:
Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
LDPC is enabled by the rate control if the its determined that the target peer supports LDPC. We would have already intersected the HT capabilities so if our peer supports LDPC so do we. Signed-off-by:
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
LDPC will be enabled through the rate control algorithm for each buffer the the tx_info flags. Signed-off-by:
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Vasanthakumar Thiagarajan authored
Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
Also add a function to clean up tx status ring. Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
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Luis R. Rodriguez authored
Enable CRC check on the descriptor fetched from host on AR9003 upon reseting the TX queue. Signed-off-by:
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Luis R. Rodriguez authored
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
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Vasanthakumar Thiagarajan authored
Also reset tx status ring suring chip reset. Signed-off-by:
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Vasanthakumar Thiagarajan authored
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
The AR9002 hardware code enables aggregation for WEP but mac80211 doesn't enable aggregation with WEP, and the AR9003 code family does not need this so skip it for now for AR9003 but leave the code and annotate we should eventually consider how to remove this in consideration for the HAL unification goals. Signed-off-by:
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Luis R. Rodriguez authored
The asynch fifo code is specific to >= AR9287 so stuff it into the AR9002 hardware family code and skip it for AR9003 cards. Signed-off-by:
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Felix Fietkau authored
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Luis R. Rodriguez authored
This is done depending on what the EEPROM settings indicates. Signed-off-by:
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Luis R. Rodriguez authored
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Vasanthakumar Thiagarajan authored
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Luis R. Rodriguez authored
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Felix Fietkau authored
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