- 14 Jun, 2024 40 commits
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Dillon Varone authored
When a phantom stream is in the process of being deconstructed, there could be pipes with no associated planes. In that case, ignore the phantom stream entirely when searching for associated pipes. Cc: stable@vger.kernel.org Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Michael Strauss authored
[WHY] Empty SST TUs are illegal to transmit over a USB4 DP tunnel. Current policy is to configure stream encoder to pack 2 pixels per pclk even when ODM combine is not in use, allowing seamless dynamic ODM reconfiguration. However, in extreme edge cases where average pixel count per TU is less than 2, this can lead to unexpected empty TU generation during compliance testing. For example, VIC 1 with a 1xHBR3 link configuration will average 1.98 pix/TU. [HOW] Calculate average pixel count per TU, and block 2 pixels per clock if endpoint is a DPIA tunnel and pixel clock is low enough that we will never require 2:1 ODM combine. Cc: stable@vger.kernel.org # 6.6+ Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Mounika Adhuri authored
[why] Move DCN3X files to unique component folder. [how] Create respective component folder in dc, move the DCN3X files into corresponding new folders and made appropriate changes for compilation in Makefiles. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Mounika Adhuri <moadhuri@amd.com> Signed-off-by:
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Chris Park authored
[Why] On init if a display is connected, we need to maintain the DISPCLK frequency Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced). [How] Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged. Reviewed-by:
Chris Park <chris.park@amd.com> Signed-off-by:
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Wenjing Liu authored
There is a coding error which causes incorrect variables to be assigned in DML21 phase 5. Reviewed-by:
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Ivan Lipski authored
[WHY] Coverity analysis this conditional code as DEADCODE. The conditional statement is never true since 'MacroTileSizeBytes' is either 256 or 65536. Thus, the code inside is the conditional statement is never reached. [HOW] Removed the conditional statement. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Alex Hung <alex.hung@amd.com> Acked-by:
Ivan Lipski <ivlipski@amd.com> Signed-off-by:
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Ivan Lipski authored
[WHY] Coverity analysis flagged this condition as DEADCODE since the variable 'req128_c' is always false, thus the condition is never true. [HOW] Remove the condition. Reviewed-by:
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Joshua Aberback authored
This reverts commit e902dd7f. A proper fix for this issue has been implemented in DMUB FW. So, no need to keep the workaround. Reviewed-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
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Relja Vojvodic authored
[Why] Found while hotplugging MST daisy chain displays. Changing dispclk during this sequence caused SMU hang due to DIG fifo not being disabled correctly (caused by missing functions). [How] Adding disable/enable DIG fifo functions for dcn401 Reviewed-by:
Relja Vojvodic <relja.vojvodic@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW] Re-enable idle optimizations by default. Reviewed-by:
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Joshua Aberback authored
[Why] During HW init, certain operations the driver performs are invalid on enabled hardware in an unknown state (for example, setting all clock values to minimum when the GPU is actively driving a display). There is already code present to call HWSS->power_down during init when any link is enabled in HW, but that function pointer is unpopulated for most asics. We want to enable this codepath for DCN401, as it resolves the issue with being unable to drive certain display configs on adapter re-enable, and we can restore boot optimizations. [How] - add power_down HWSS function for DCN401 - remove debug bit to disable boot optimizations for DCN401 Reviewed-by:
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Yang Wang authored
refine gfx8 firmware loading Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Tao Zhou authored
GFX v9.4.3 uses mode1 reset, other ASICs choose mode2. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Tao Zhou authored
Per firmware's requirement, replace mode2 with mode1. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
The fed status does indicate RAS fatal error. Signed-off-by:
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Tao Zhou authored
Indicate fatal error for each RAS block and NBIO. Signed-off-by:
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Tao Zhou authored
Reduce redundant code and user doesn't need to pay attention to RAS details. Signed-off-by:
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Tao Zhou authored
Check RMA status in bad page retirement flow. v2: fix coding bugs in v1. Signed-off-by:
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Daniel Miess authored
[Why] PHYSYMCLK RCO has been found to lead to crashes in some corner cases [How] Disable PHYSYMCLK RCO debug bit Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
- Create a general command and fix Replay desync error with general cmd Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Aric Cyr authored
* FW Release 0.0.221.0 * Fixed missing targets in FAMS2 * Populate hardware_release hook for dcn401 * Disable DMCUB timeout for DCN35 * Move PRIMARY plane zpos higher * Introduce overlay cursor mode * Change dram_clock_latency for dcn35 and dcn351 * DCN401 cursor code update Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] Update the idle hardmin with SMU if either clock changed. Reviewed-by:
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Alex Hung authored
[WHAT & HOW] dmub_rb_cmd's ramping_boundary has size of uint8_t and it is assigned 0xFFFF. Fix it by changing it to uint8_t with value of 0xFF. This fixes 2 INTEGER_OVERFLOW issues reported by Coverity. Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Acked-by:
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Dillon Varone authored
[WHY&HOW] Reinit should return after completing version 2.1 reinit instead of calling version 2 reinit after. Reviewed-by:
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Dillon Varone authored
[WHY&HOW] Add additional delay factor when considering a safe time to flip for HWFQ to be passed in by the driver. Reviewed-by:
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Dillon Varone authored
[WHY&HOW] Sometimes this function is called with a partially deconstructed phantom stream toplolgy, and should ignore phantoms with no plane state. Reviewed-by:
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Dillon Varone authored
[WHY&HOW] SubVP is not supported when hardware rotation is in use. Reviewed-by:
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Alex Hung authored
[WHY & HOW] v_total is an uint32_t and subtracting an unsigned to a signed will result in an unsigned which is always >= 0. As a result, the ternary conditions are always true and thus has no effect. This is fixed by casting v_total to signed explicitly. This also avoids v_total subtraction to overflow. This fixes 1 NO_EFFECT, 2 DEADCODE and 2 INTEGER_OVERFLOW issues reported by Coverity. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Alex Hung authored
[WHAT & HOW] The self-assignments have no effects and thus are removed. Reviewed-by:
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Ivan Lipski authored
[WHY] Coverity analysis of the Upstream display driver code (amd-staging-drm-next) flagged these three functions as containing 'CONSTANT_EXPRESSION_RESULT' errors, i. e. the conditionals are reduntant since their result is predetermined. fixpt31_32.c: The two flagged 'ASSERT' lines redundant since they are always true: - LONG_MAX equals to the largest 'signed long long' number - res.value is type 'signed long long', So, the condition inside the 'ASSERTS's is always link_dp_training.c: The flagged conditional statement is always false: - 'max_requested.FFE_PRESET.settings.level' is 4 bits, so its max possible value is 15 - 'DP_FFE_PRESET_MAX_LEVEL' equals to 15. So, the conditional statement is always false and the wrapped code never executes. [HOW] Removed lines flagged by Coverity analysis. Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
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Alvin Lee authored
[Description] hardare_release() is called when driver is removed. Add the missing hook for DCN401 Reviewed-by:
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Wenjing Liu authored
[why] In YCbCr422 format hardware shares 1 set of chromas CbCr with 2 sets of lumas Y. Therefore each ODM segment needs to be two pixel aligned. The commit adds this missing hardwware requirement into ODM segment width decision logic. Reviewed-by:
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JinZe.Xu authored
[Why&How] Add flag to disable IPS when it is not allowed. Reviewed-by:
JinZe.Xu <jinze.xu@amd.com> Tested-by:
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Sung-huai Wang authored
[How&Why] This reverts commit 239b31bd. Due to the it effects Replay resync. Reviewed-by:
Sung-huai Wang <danny.wang@amd.com> Tested-by:
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Alex Hung authored
[WHY & HOW] The comparisons of unsigned int with 0 can have no meanings, i.e. unsigned int >= 0 (always true) or unsigned int < 0 (always false), and therefore they are removed. This fixes 12 NO_EFFECT issues reported by Coverity. Reviewed-by:
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Alex Hung authored
This fixes an UNINIT issue reported by Coverity. Reviewed-by:
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Alex Hung authored
[WHY] fe_clk_en and be_clk_sel have size of 4 but sizeof(fe_clk_en) has byte size 16 which is lager than the array size. [HOW] Use ARRAY_SIZE for calculating size. This fixes 2 OVERRUN issues reported by Coverity. Reviewed-by:
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Sridevi Arvindekar authored
Move pipe_ctx variables to start of the function and add a helpful comment Co-authored-by:
Sridevi Arvindekar <sarvinde@amd.com> Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Acked-by:
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Rodrigo Siqueira authored
Coverity highlighted that the parameter otg_master is referenced before the if condition that validates it, which means that the code might have some attempt to access a null pointer. This commit addresses this issue by moving the pointer verification to the beginning of the function and initializing all the values right after it. Acked-by:
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Nicholas Kazlauskas authored
[Why] DMCUB can intermittently take longer than expected to process commands. Old ASIC policy was to continue while logging a diagnostic error - which works fine for ASIC without IPS, but with IPS this could lead to a race condition where we attempt to access DCN state while it's inaccessible, leading to a system hang when the NIU port is not disabled or register accesses that timeout and the display configuration in an undefined state. [How] We need to investigate why these accesses take longer than expected, but for now we should disable the timeout on DCN35 to avoid this race condition. Since the waits happen only at lower interrupt levels the risk of taking too long at higher IRQ and causing a system watchdog timeout are minimal. Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Acked-by:
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