- 15 Jun, 2017 24 commits
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Harish Kasiviswanathan authored
Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Harish Kasiviswanathan authored
CPU and GPU paths were mostly the same. Acked-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Tom St Denis authored
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Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
Allows reading/writing via SOC15 macros with offset for various register banks. Signed-off-by:
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Eric Huang authored
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Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Alex Deucher authored
Same as other asics. If enabled, exposes a user selectable number of virtual displays. Reviewed-by:
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Alex Deucher authored
This got lost when the code was revamped. Copy/paste bug from gfx8. Reported-by:
Evan Quan <evan.quan@amd.com> Fixes: 78c16834 (drm/amdgpu: allow split of queues with kfd at queue granularity v4) Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Tom St Denis authored
Swap space for underscore in ring name. Signed-off-by:
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Tom St Denis authored
A couple of simple tidy ups to register programming. Signed-off-by:
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horchen authored
Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary. Signed-off-by:
horchen <horace.chen@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
gpu_info firmware is released after data is used. But when system enters into suspend, upper class driver will cache all firmware names. At that time, gpu_info will be failing to load. It seems an upper class issue, that we should not release gpu_info firmware until device finished. [ 903.236589] cache_firmware: amdgpu/vega10_sdma1.bin [ 903.236590] fw_set_page_data: fw-amdgpu/vega10_sdma1.bin buf=ffff88041eee10c0 data=ffffc90002561000 size=17408 [ 903.236591] cache_firmware: amdgpu/vega10_sdma1.bin ret=0 [ 903.464160] __allocate_fw_buf: fw-amdgpu/vega10_gpu_info.bin buf=ffff88041eee2c00 [ 903.471815] (NULL device *): loading /lib/firmware/updates/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.482870] (NULL device *): loading /lib/firmware/updates/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.492716] (NULL device *): loading /lib/firmware/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.503156] (NULL device *): direct-loading amdgpu/vega10_gpu_info.bin Signed-off-by:
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Huang Rui authored
As Christian and David's suggestion, submit the test ib ring debug interfaces. It's useful for debugging with the command submission without VM case. Signed-off-by:
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Eric Huang authored
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Eric Huang authored
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Hawking Zhang authored
No need to clear it. The values are set explicitly. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
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- 09 Jun, 2017 9 commits
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Alex Deucher authored
The interrupt registers are not indexed. Fixes: 763a47b8 (drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v3) Acked-by:
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Rex Zhu authored
v2: fix typos. should disable led dpm feature when stop dpm. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Alex Xie authored
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Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
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Alex Xie authored
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Alex Xie authored
There are two identical function prototypes in same header file Signed-off-by:
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Harish Kasiviswanathan authored
v2: Fix logical mistake. If CPU update failed amdgpu_vm_bo_update_mapping() would not return and instead fall through to SDMA update. Minor change due to amdgpu_vm_bo_wait() prototype change Signed-off-by:
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Harish Kasiviswanathan authored
If amdgpu.vm_update_context param is set to use CPU, then Page Directories will be updated by CPU instead of SDMA v2: Call amdgpu_vm_bo_wait before updating the page tables to ensure the PD/PT BOs are free v3: Minor changes - due to amdgpu_vm_bo_wait() prototype change, local variable declaration order and function comments. Signed-off-by:
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Harish Kasiviswanathan authored
v2: Add intr option Helper function useful for CPU update of VM page tables. Also useful if kernel have to synchronously wait till VM page tables are updated. Signed-off-by:
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Harish Kasiviswanathan authored
Add VM update mode module param (amdgpu.vm_update_mode) that can used to control how VM pde/pte are updated for Graphics and Compute. BIT0 controls Graphics and BIT1 Compute. BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU BIT1 [= 0] Compute updated by SDMA [= 1] by CPU By default, only for large BAR system vm_update_mode = 2, indicating that Graphics VMs will be updated via SDMA and Compute VMs will be updated via CPU. And for all all other systems (by default) vm_update_mode = 0 Signed-off-by:
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- 08 Jun, 2017 7 commits
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Alex Deucher authored
Open code them so we can adjust the order in the driver more easily. Reviewed-by:
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Alex Deucher authored
Rather than calling the deprecated drm_pci_init() and drm_pci_exit() which just wrapped the pci functions anyway. Reviewed-by:
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Michel Dänzer authored
Even if CONFIG_DRM_AMDGPU_CIK is enabled. There is no feature parity yet for CIK, in particular amdgpu doesn't support HDMI/DisplayPort audio without DC. v2: * Clarify the lack of feature parity being related to HDMI/DP audio. * Fix "SI" typo in DRM_AMDGPU_CIK help entry. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com>
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Michel Dänzer authored
This will allow amdgpu-pro / other out-of-tree amdgpu builds to make use of these options for using the out-of-tree amdgpu driver instead of the in-tree radeon driver in a clean way. Reviewed-by:
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Felix Kuehling authored
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Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Felix Kuehling authored
If AMDGPU supports SI, add a module parameter to control SI support. It's off by default in AMDGPU as long as SI suppost is experimental, while it is on by default in radeon. Signed-off-by:
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Felix Kuehling authored
If AMDGPU supports SI, add a module parameter to control SI support in radeon. It's on by default in radeon, while it will be off by default in AMDGPU as long as SI support is experimental. Signed-off-by:
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