- 02 Nov, 2021 1 commit
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Stephen Boyd authored
- Use ARRAY_SIZE in qcom clk drivers - Remove some impractical fallback parent names in qcom clk drivers - GCC and RPMcc support for Qualcomm QCM2290 SoCs - GCC support for Qualcomm MSM8994/MSM8992 SoCs - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs - Support for Mediatek MT8195 SoCs - Make Mediatek clk drivers tristate * clk-qcom: (44 commits) clk: qcom: gdsc: enable optional power domain support clk: qcom: videocc-sm8250: use runtime PM for the clock controller clk: qcom: dispcc-sm8250: use runtime PM for the clock controller dt-bindings: clock: qcom,videocc: add mmcx power domain dt-bindings: clock: qcom,dispcc-sm8x50: add mmcx power domain clk: qcom: gcc-sc7280: Drop unused array clk: qcom: camcc: Add camera clock controller driver for SC7280 dt-bindings: clock: Add YAML schemas for CAMCC clocks on SC7280 clk: qcom: Add lpass clock controller driver for SC7280 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280 clk: qcom: Kconfig: Sort the symbol for SC_LPASS_CORECC_7180 clk: qcom: mmcc-sdm660: Add hw_ctrl flag to venus_core0_gdsc clk: qcom: mmcc-sdm660: Add necessary CXCs to venus_gdsc clk: qcom: gcc-msm8994: Use ARRAY_SIZE() for num_parents clk: qcom: gcc-msm8994: Add proper msm8992 support clk: qcom: gcc-msm8994: Add modem reset clk: qcom: gcc-msm8994: Remove the inexistent GDSC_PCIE clk: qcom: gcc-msm8994: Add missing clocks clk: qcom: gcc-msm8994: Add missing NoC clocks clk: qcom: gcc-msm8994: Fix up SPI QUP clocks ... * clk-mtk: (28 commits) clk: mediatek: Export clk_ops structures to modules clk: mediatek: support COMMON_CLK_MT6779 module build clk: mediatek: support COMMON_CLK_MEDIATEK module build clk: composite: export clk_register_composite clk: mediatek: Add MT8195 apusys clock support clk: mediatek: Add MT8195 imp i2c wrapper clock support clk: mediatek: Add MT8195 wpesys clock support clk: mediatek: Add MT8195 vppsys1 clock support clk: mediatek: Add MT8195 vppsys0 clock support clk: mediatek: Add MT8195 vencsys clock support clk: mediatek: Add MT8195 vdosys1 clock support clk: mediatek: Add MT8195 vdosys0 clock support clk: mediatek: Add MT8195 vdecsys clock support clk: mediatek: Add MT8195 scp adsp clock support clk: mediatek: Add MT8195 mfgcfg clock support clk: mediatek: Add MT8195 ipesys clock support clk: mediatek: Add MT8195 imgsys clock support clk: mediatek: Add MT8195 ccusys clock support clk: mediatek: Add MT8195 camsys clock support clk: mediatek: Add MT8195 infrastructure clock support ... * clk-versatile: clk: versatile: hide clock drivers from non-ARM users clk: versatile: Rename ICST to CLK_ICST clk: versatile: clk-icst: Support 'reg' in addition to 'vco-offset' for register address dt-bindings: clock: arm,syscon-icst: Use 'reg' instead of 'vco-offset' for VCO register address * clk-doc: dt-bindings: clk: fixed-mmio-clock: Convert to YAML
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- 15 Oct, 2021 7 commits
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Jean Delvare authored
Commit 419b3ab6 ("clk: versatile: remove dependency on ARCH_*") made the whole menu of ARM reference clock drivers visible on all architectures. I can't see how this is an improvement for non-ARM users. Unless build-testing, there is no point on presenting ARM-only clock drivers on other architectures. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: Peter Collingbourne <pcc@google.com> Cc: Lee Jones <lee.jones@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210901180953.5bd2a994@endymionReviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Jean Delvare authored
For consistency, prefix the ICST config option with CLK as all other clock source drivers have. Signed-off-by:
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Dmitry Baryshkov authored
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we use a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Make gdsc code also use pm_runtime calls to ensure that registers are accessible during the gdsc_enable/gdsc_disable operations. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210829154757.784699-6-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by:
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Dmitry Baryshkov authored
On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Use runtime PM calls to make sure that required power domain is powered on while we access clock controller's registers. Signed-off-by:
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Dmitry Baryshkov authored
On sm8250 videocc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210829154757.784699-3-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by:
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- 14 Oct, 2021 1 commit
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Stephen Boyd authored
After commit 3165d1e3 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280") this array is unused. Remove it. Reported-by:
kernel test robot <lkp@intel.com> Cc: Taniya Das <tdas@codeaurora.org> Fixes: 3165d1e3 ("clk: qcom: gcc: Remove CPUSS clocks control for SC7280") Link: https://lore.kernel.org/r/20211014191259.1689641-1-sboyd@kernel.orgSigned-off-by:
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- 13 Oct, 2021 21 commits
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Taniya Das authored
Add support for the camera clock controller found on SC7280 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by:
Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1633567425-11953-2-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Make some VCOs unsigned long] Signed-off-by:
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Taniya Das authored
The camera clock controller clock provider have a bunch of generic properties that are needed in a device tree. Add the CAMCC clock IDs for camera client to request for the clocks. Signed-off-by:
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Taniya Das authored
Add support for the lpass clock controller found on SC7280 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. Signed-off-by:
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Taniya Das authored
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Add the LPASS clock IDs for LPASS PIL client to request for the clocks. Signed-off-by:
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Taniya Das authored
Fix the order of the Kconfig symbol for SC_LPASS_CORECC_7180. Signed-off-by:
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AngeloGioacchino Del Regno authored
As shown downstream[1], this GDSC supports HW trigger mode and we're supposed to enable it in order to ensure correct operation. [1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm630.dtsi#L2181Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20211008102041.268253-2-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
As also shown on downstream dts[1], for a correct operation of the Venus block, we have to retain MEM/PERIPH when halting the video_core, video_axi and video_subcore0 branches: add these CXCs to the main Venus GDSC. [1]: https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi#L80Signed-off-by:
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Konrad Dybcio authored
Don't rely on the programmer to enter the name of array elements, since the computer can compute it with much less chance of making a mistake. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210923162645.23257-9-konrad.dybcio@somainline.orgSigned-off-by:
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Konrad Dybcio authored
MSM8992 is a cut-down version of MSM8994, featuring largely the same hardware. Signed-off-by:
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Konrad Dybcio authored
This will be required to support the modem. Signed-off-by:
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Konrad Dybcio authored
This GDSC is not present on msm8994. Signed-off-by:
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Konrad Dybcio authored
This should be the last "add missing clocks" commit, as to my knowledge there are no more clocks registered within gcc. Signed-off-by:
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Konrad Dybcio authored
Add necessary NoC clocks to provide frequency sources for relevant branch clocks. Signed-off-by:
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Konrad Dybcio authored
Fix up SPI QUP freq tables to account for the fact that not every QUP can run at the same set of frequencies. Signed-off-by:
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Konrad Dybcio authored
Switch to the newer-style parent_data and remove the hardcoded xo clock. Signed-off-by:
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Konrad Dybcio authored
Add documentation for the MSM8994 GCC driver. While at it, retire its compatible from the old, everyone-get-in-here file. Signed-off-by:
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Shawn Guo authored
Add support for RPM-managed clocks on the QCM2290 platform. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210917030434.19859-4-shawn.guo@linaro.orgReviewed-by:
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Shawn Guo authored
Add compatible for the RPM Clock Controller on the QCM2290 SoC. Signed-off-by:
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Shawn Guo authored
As there is a `rate` field in clk_smd_rpm, clk_smd_rpm_recalc_rate() can be used by branch clocks to report rate as well, rather than assuming the rate is always same as parent clock. This assumption doesn't hold on platforms like QCM2290, where xo_board is 38.4MHz while bi_tcxo is 19.2MHz. To get this work, XO buffered clocks need the following updates. - Assign a correct rate rather than the fake one which is being used to generate binary value for clk_smd_rpm_req interface. - Explicitly handle the clk_smd_rpm_req interface value for XO buffered clocks (.rpm_res_type being QCOM_SMD_RPM_CLK_BUF_A). Suggested-by:
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Shawn Guo authored
Add Global Clock Controller (GCC) driver for QCM2290. This is a porting of gcc-scuba driver from CAF msm-4.19, with GDSC support added on top. Because the alpha_pll on the platform has a different register layout (offsets), its own clk_alpha_pll_regs_offset[] is used in the driver. Signed-off-by:
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Shawn Guo authored
It adds device tree bindings for QCM2290 Global Clock Controller. Signed-off-by:
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- 08 Oct, 2021 2 commits
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Taniya Das authored
The CPUSS clocks are kept always ON and at a fixed frequency of 100MHZ from the bootloader and no longer required to be controlled from HLOS. Fixes: a3cc0921 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280") Signed-off-by:
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Kai Song authored
Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by:
Kai Song <songkai01@inspur.com> Link: https://lore.kernel.org/r/20211006043627.5125-1-songkai01@inspur.comSigned-off-by:
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- 15 Sep, 2021 7 commits
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Stephen Boyd authored
modpost complains once these drivers become modules. ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined! Let's just export them. Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Cc: Miles Chen <miles.chen@mediatek.com> Fixes: 32b028fb ("clk: mediatek: support COMMON_CLK_MEDIATEK module build") Link: https://lore.kernel.org/r/20210915015540.1732014-1-sboyd@kernel.orgSigned-off-by:
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Miles Chen authored
To support COMMON_CLK_MT6779* module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210901222526.31065-4-miles.chen@mediatek.comSigned-off-by:
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Miles Chen authored
To support COMMON_CLK_MEDIATEK module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by:
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Miles Chen authored
To support module build of mediatek clk drivers, it is necessary to export clk_register_composite. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by:
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Marek Behún authored
Convert the binding documentatoin for fixed-mmio-clock to YAML. Signed-off-by:
Marek Behún <kabel@kernel.org> Link: https://lore.kernel.org/r/20210903152615.31453-1-kabel@kernel.orgReviewed-by:
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Rob Herring authored
The ICST binding now also supports 'reg' in addition to 'vco-offset' for the VCO register address. Add support to the driver to get the VCO address from 'reg'. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Signed-off-by:
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Rob Herring authored
'reg' is the standard property for defining register banks/addresses. Add it to use for the VCO register address and deprecate 'vco-offset'. This will also allow for using standard node names with unit-addresses. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by:
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- 14 Sep, 2021 1 commit
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Chun-Jie Chen authored
Add MT8195 apusys clock controller which provides PLLs in AI processor Unit. Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-25-chun-jie.chen@mediatek.comSigned-off-by:
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