- 13 Mar, 2023 40 commits
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AngeloGioacchino Del Regno authored
In order to successfully build clock drivers as modules it is required to declare a module license: add it where missing. While at it, also change the MODULE_LICENSE text from "GPL v2" to "GPL" (which means the same) on clk-mt7981-eth.c. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Chen-Yu Tsai <wenst@chromium.org> Tested-by:
Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-38-angelogioacchino.delregno@collabora.comSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
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AngeloGioacchino Del Regno authored
Lots of clock drivers have got both .probe() and a .remove() callbacks: switch from builtin_platform_driver() to module_platform_driver() so that we actually register the .remove() callback. Signed-off-by:
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AngeloGioacchino Del Regno authored
Convert MT8186 MCUSYS clocks to the common mtk_clk_simple_probe(). Signed-off-by:
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AngeloGioacchino Del Regno authored
Convert this driver to use the common mtk_clk_simple_probe() mechanism. While at it, also remove __initconst annotations (as these structures are used also at runtime). Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/20230306140543.1813621-35-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Convert this driver to use the common mtk_clk_simple_probe() mechanism. While at it, also use module_platform_driver() instead, as this driver just gained a .remove() callback during the conversion. Signed-off-by:
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AngeloGioacchino Del Regno authored
Instead of calling clk_prepare_enable() at probe time, add the PLL_AO flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL. Signed-off-by:
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AngeloGioacchino Del Regno authored
Propagate struct device for divider clocks registered through clk-mtk helpers to be able to get runtime PM support for MTK clocks. Signed-off-by:
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AngeloGioacchino Del Regno authored
Now that all MT8516 drivers have been converted to platform driver, change the configuration options to tristate. Signed-off-by:
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AngeloGioacchino Del Regno authored
Convert the MT8516 clock drivers to be platform drivers and use the common probe mechanism. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for migrating mt8516 clocks to the common simple probe mechanism, convert the apmixedsys to be a separated platform driver and move it to clk-mt8516-apmixedsys.c. While at it, also fix some indentation issues. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
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AngeloGioacchino Del Regno authored
Convert the MT7622 topckgen and pericfg clock drivers to platform drivers and use the simple probe mechanism. This also allows to build these clocks as modules. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by:
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AngeloGioacchino Del Regno authored
The infracfg driver cannot be converted to clk_mtk_simple_probe() as it registers cpumuxes, which is not supported on the common probing mechanism: for this reason, move it to its own file. While at it, also convert it to be a platform driver instead; to do so, also add a .remove() callback for this driver. During the conversion, error handling was added to the infracfg probe function. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add a .remove() callback to the apmixedsys driver to allow full module build; while at it, also change the usage of builtin_platform_driver() to module_platform_driver() to actually make use of the new callback. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for migrating mt7622 clocks to the common simple probe mechanism, move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
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AngeloGioacchino Del Regno authored
Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: 2fc0a509 ("clk: mediatek: add clock support for MT7622 SoC") Signed-off-by:
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AngeloGioacchino Del Regno authored
All the various MediaTek clock drivers are, in a way or another, redefining the GATE_MTK() macro with different names: while some are doing that by actually using GATE_MTK(), others are copying it entirely (hence, entirely redefining it). Change all clock drivers to always and consistently use this macro. Signed-off-by:
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AngeloGioacchino Del Regno authored
Switch to mtk_clk_simple_{probe,remove}() for infracfg and topckgen clocks on MT8183 to allow full module build for clock drivers. Differently from other MediaTek clock drivers, it was necessary to change the name of the `clk13m` clock, as that is already declared in the SoC's devicetree as a "fixed-factor-clock" (with the same name) and redeclaring it here would obviously fail to register the entire clock controller; this clock wasn't dropped only to retain compatibility with older devicetrees As a note, the `clk13m` clock is not mentioned in any parent names array(s) as the correct one (csw_f26m_d2) is already used in place of that. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: -
AngeloGioacchino Del Regno authored
Increase human readability and decrease number of lines by compressing the clock array entries where possible, to a maximum of ~95 columns. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for migrating all other mt8183 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it and fix some indentation issues in the PLLs table. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
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AngeloGioacchino Del Regno authored
Convert topckgen and infracfg clock drivers to use the common mtk_clk_simple_probe() mechanism and change this from the old "static" CLK_OF_DECLARE to be a platform driver, allowing it to eventually be built as a module. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for converting the MT8167 clock drivers to be proper platform_driver(s), drop the __initconst annotation from all of the clock arrays since they will be used not only during init but also during runtime. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for migrating all other MT8167 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, also migrate away from the legacy CLK_OF_DECLARE and convert this clock driver to be a platform_driver instead. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
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AngeloGioacchino Del Regno authored
Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros. No functional changes. Signed-off-by: -
AngeloGioacchino Del Regno authored
All clocks in this driver are supported by the common simple probe mechanism and it's now possible to migrate to it. While at it, also switch to using the module_platform_driver() macro. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for migrating this driver to the simple probe mechanism, join the audio gates to the top_misc_mux_gates array of mtk_composite clocks in one top_misc_muxes array. While at it, since the `apll_i2s0_parents` array is for all i2s clocks, rename that to `apll_i2s_parents`. Signed-off-by:
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AngeloGioacchino Del Regno authored
On this SoC some clocks apparently don't have different offsets for set/clr/sta registers hence they can be set, cleared and status-read on one register: this means that it was possible to use simpler gate clocks instead of custom mtk_gate ones. In preparation for converting this clock driver to the common probe mechanism for MediaTek clocks, perform a conversion from simple_gate to mtk_gate clocks since the latter does provide implicit support for simple gate clocks as well. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for migrating all other mt8365 clocks to the common mtk_clk_simple_probe(), move apmixedsys clocks to a different file. While at it, use the builtin_platform_driver() macro for it. During the conversion, error handling was added to the apmixedsys probe function. Signed-off-by:
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AngeloGioacchino Del Regno authored
Now that all of the clocks in clk-mt2712.c are using the common mtk_clk_simple_{probe,remove}() callbacks we can safely migrate to module_platform_driver. While at it, also drop all references to `simple` in the specific context of mt2712 as that was used in the past only to allow us to have two platform_driver(s) in one file. Signed-off-by: -
AngeloGioacchino Del Regno authored
Add a .remove() callback to the apmixedsys driver to allow full module build; while at it, also change the usage of builtin_platform_driver() to module_platform_driver() to actually make use of the new callback. Signed-off-by:
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AngeloGioacchino Del Regno authored
The only clock driver that does not support mtk_clk_simple_probe() is apmixedsys: in preparation for enabling module build of non-critical mt2712 clocks, move this to its own file. While at it, also fix some indentation issues in the PLLs table. Signed-off-by:
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AngeloGioacchino Del Regno authored
This function was completely missing error handling: add it. Fixes: e2f744a8 ("clk: mediatek: Add MT2712 clock support") Signed-off-by:
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AngeloGioacchino Del Regno authored
Compress the clock arrays entries to allow a maximum of 90 columns: this greatly increases readability and also generously reduces the amount of lines. While at it, also fix some indentation here and there. This is a cosmetic change. No functional changes. Signed-off-by:
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AngeloGioacchino Del Regno authored
Now that the common mtk_clk_simple_{probe,remove}() functions can deal with divider clocks it is possible to migrate more clock drivers to it: in this case, it's about topckgen. While at it, also perform a fast migration for mcucfg. Thanks to the conversion, more error handling was added to the clocks registration. Signed-off-by: -
AngeloGioacchino Del Regno authored
Add support for divider clocks register/unregister in the common mtk_clk_simple_probe() and mtk_clk_simple_remove() functions. Signed-off-by:
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AngeloGioacchino Del Regno authored
Reduce duplication and simplify all MediaTek multimedia clock drivers by migrating away from defining custom probe functions for each driver and instead use mtk_clk_pdev_probe(). While at it, also add a .remove() callback to all of the multimedia clock drivers where missing. Signed-off-by:
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AngeloGioacchino Del Regno authored
Introduce functions clk_mtk_pdev_probe() and clk_mtk_pdev_remove(): these will be useful to commonize the probe and remove handlers for multimedia (clk-mtxxxx-mm) drivers as these are registered by the mtk-mmsys driver instead of having their own devicetree compatible. In order to do this, the main logic of clk_mtk_simple{probe,remove}() was moved to new static __clk_mtk_simple_{probe,remove}() functions that take as parameter a pointer to struct device_node because when registering the clocks from mtk-mmsys we want to pass a pointer to the clock driver's parent (which is, obviously, mtk-mmsys) struct device_node instead. As for the clock driver's platform data: for the devicetree case, we keep using the standard match_data mechanism, else we retrieve it from an id_table. Signed-off-by: -
AngeloGioacchino Del Regno authored
Instead of using of_device_get_match_data(), switch to the generic device_get_match_data(). Signed-off-by:
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AngeloGioacchino Del Regno authored
Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by:
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