- 22 Jun, 2023 1 commit
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Rob Herring authored
The conditional if/then schema has an error as the "enum" values have "const" in them. Drop the "const". Signed-off-by:
Rob Herring <robh@kernel.org> Fixes: 46b616c1 ("dt-bindings: phy: brcm, brcmstb-usb-phy: add BCM4908 binding") Acked-by:
Rafał Miłecki <rafal@milecki.pl> Message-ID: <20230621230958.3815818-1-robh@kernel.org> Signed-off-by:
Vinod Koul <vkoul@kernel.org>
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- 21 Jun, 2023 13 commits
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Alexander Stein authored
With dt-schema v2021.02 these properties are added by default. Some SoC (e.g. imx8mq) configure more than just one clock using these properties. Fixes: f9b0593d ("dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema") Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230609071538.149712-1-alexander.stein@ew.tq-group.comSigned-off-by:
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Krzysztof Kozlowski authored
Make the pattern matching node names a bit stricter to improve DTS consistency. The pattern is restricted to: 1. Only one unit address or one -N suffix, 2. -N suffixes to decimal numbers. Suggested-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Tony Lindgren <tony@atomide.com> Reviewed-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230530144851.92059-2-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Rudraksha Gupta authored
Adds qcom,usb-hs-phy-msm8960 compatible Signed-off-by:
Rudraksha Gupta <guptarud@gmail.com> Reviewed-by:
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Claudiu Beznea authored
devm_kzalloc() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: f67213ce ("phy: tegra: xusb: Add usb-role-switch support") Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230531073950.145339-1-claudiu.beznea@microchip.comSigned-off-by:
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Neil Armstrong authored
The SM8550 PHY also uses a different offset for the CMN_STATUS reg, use the right one for the v6 Display Port configuration. Fixes: 49742e9e ("phy: qcom-qmp-combo: Add support for SM8550") Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-dp-phy-init-fix-v1-1-4e9da9f97991@linaro.orgSigned-off-by:
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Bartosz Golaszewski authored
Implement support for the SGMII/SerDes PHY present on various Qualcomm platforms. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20230619091336.194914-4-brgl@bgdev.plSigned-off-by:
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Bartosz Golaszewski authored
Describe the SGMII/SerDes PHY present on the sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Align all entries in Makefile. Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230619091336.194914-2-brgl@bgdev.plSigned-off-by:
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Justin Chen authored
We hit a false positive OC for 7439b2 in DRD/device mode for the second port. So disable the OC check for this use case. Add capability to suppress OC condition for specific ports. Signed-off-by:
Justin Chen <justin.chen@broadcom.com> Reviewed-by:
Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/1686859578-45242-3-git-send-email-justin.chen@broadcom.comSigned-off-by:
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Justin Chen authored
The COMMONONN bit turns off the PHY when the host controller puts it into suspend state. This can happen during the following... - Nothing is connected to the port - The host controller goes into low power mode whatever due to auto suspend or system suspend. With COMMONONN we also must unset U2_FREECLK_EXISTS since the UTMI clock is fed by the PHY. With these changes we see a power savings of ~12mW when port is in suspend. Reviewed-by:
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EJ Hsu authored
For the dual-role port, it will assign the phy dev to usb-phy dev and use the port dev driver as the dev driver of usb-phy. When we try to destroy the port dev, it will destroy its dev driver as well. But we did not remove the reference from usb-phy dev. This might cause the use-after-free issue in KASAN. Fixes: e8f7d2f4 ("phy: tegra: xusb: Add usb-phy support") Cc: stable@vger.kernel.org Signed-off-by:
EJ Hsu <ejh@nvidia.com> Signed-off-by:
Haotien Hsu <haotienh@nvidia.com> Acked-by:
Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230609062932.3276509-1-haotienh@nvidia.comSigned-off-by:
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Xu Yang authored
The imx8ulp and imx8qm are compatible with imx8dxl. This will add such compatible. Signed-off-by:
Xu Yang <xu.yang_2@nxp.com> Acked-by:
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Xu Yang authored
Convert the binding to DT schema format. Besides, this also add clocks, '#phy-cells', phy-3p0-supply and power-domains properties which are not contained in txt file due to txt file lack updates. Signed-off-by:
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- 30 May, 2023 1 commit
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Dmitry Baryshkov authored
Merge two allOf clauses, which sneaked in in two different patches. Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml:109:1: found duplicate key "allOf" with value "[]" (original value: "[]") Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml:109:1: [error] duplication of key "allOf" in mapping (key-duplicates) Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml:109:1: found duplicate key "allOf" with value "[]" (original value: "[]") Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml: ignoring, error parsing file Fixes: 2daece5e ("dt-bindings: phy: qcom,qmp-usb: Drop legacy bindings and move to newer one (SM6115 & QCM2290)") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20230521195200.11967-1-dmitry.baryshkov@linaro.orgSigned-off-by:
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- 24 May, 2023 2 commits
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Vinod Koul authored
sc8180x ufs phy requires to describe five reg areas for the phy to work, so move the description to the correct place documenting tx, rx lane 1, 2 and pcs. Acked-by:
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Vinod Koul authored
sc8180x pcie phy requires to describe six reg areas for the phy to work, so move the description to the correct place documenting tx, rx lane 1, 2 and pcs and pcs misc. Acked-by:
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- 19 May, 2023 17 commits
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Chunfeng Yun authored
These debugfs files are mainly used to make eye diagram test easier, especially helpful to do HQA test for a new IC without efuse enabled. Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230513092218.21139-2-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
Add a debugfs root for phy class, and create a debugfs directory under the root when create phy, then phy drivers can add debugfs files. Signed-off-by:
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Li Jun authored
Add USB PHY parameter tuning for USB certifications. Reviewed-by:
Haibo Chen <haibo.chen@nxp.com> Signed-off-by:
Li Jun <jun.li@nxp.com> [j.zink: ported to v6.3-rc1 from NXP downstream repo + cleanups] Signed-off-by:
Johannes Zink <j.zink@pengutronix.de> Link: https://lore.kernel.org/r/20230516-lustige-usb-phy-dinge-v2-2-3383a0de34ac@pengutronix.deSigned-off-by:
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Johannes Zink authored
Add optional properties for tuning of usb phy. Signed-off-by:
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Bjorn Andersson authored
The QMP combo PHY sits in an of_graph connected between the DisplayPort controller and a USB Type-C connector (or possibly a redriver). The TCPM needs to be able to convey the HPD signal to the DisplayPort controller, but no directly link is provided by DeviceTree so the signal needs to "pass through" the QMP combo phy. Handle this by introducing a drm_bridge which upon initialization finds the next bridge (i.e. the usb-c-connector) and chain this together. This way HPD changes in the connector will propagate to the DisplayPort driver. The connector bridge is resolved lazily, as the TCPM is expected to be able to resolve the typec mux and switch at probe time, so the QMP combo phy will probe before the TCPM. Acked-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Tested-by:
Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-7-quic_bjorande@quicinc.comSigned-off-by:
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Bjorn Andersson authored
The data lanes of the QMP PHY is swapped in order to handle changing orientation of the USB Type-C cable. Register a typec_switch device to allow a TCPM to configure the orientation. The newly introduced orientation variable is adjusted based on the request, and the initialized components are brought down and up again. To keep track of what parts needs to be cycled new variables to keep track of the individual init_count is introduced. Both the USB and the DisplayPort altmode signals are properly switched. For DisplayPort the controller will after the TCPM having established orientation power on the PHY, so this is not done implicitly, but for USB the PHY typically is kept initialized across the switch, and must therefore then be reinitialized. This is based on initial work by Wesley Cheng. Link: https://lore.kernel.org/r/20201009082843.28503-3-wcheng@codeaurora.org/Reviewed-by:
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Bjorn Andersson authored
In multiple places throughout the driver code has been written in prepration for handling of orientation switching. Introduce a typec_orientation in qmp_combo and fill out the various "placeholders" with the associated logic. By initializing the orientation to "normal" this change has no functional impact, but reduces the size of the upcoming introduction of dynamic orientation switching. Reviewed-by:
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Bjorn Andersson authored
The phy core ensures mutual exclusion across the ops for a given phy, but the upcoming introduction of USB Type-C orientation switching might race with the DisplayPort phy operations. So extend the mutual exclusion to cover the remaining ops as well, to avoid concurrent reconfiguration of the hardware. Reported-by:
Johan Hovold <johan@kernel.org> Reviewed-by:
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Bjorn Andersson authored
With the upcoming introduction of USB Type-C orientation switching the region of mutual exclusion needs to be extended to cover both the common init/exit as well as the individual functions. So move the phy_mutex one step up the stack. Reviewed-by:
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Bjorn Andersson authored
The QMP combo phy can be connected to a TCPM, a USB controller and a DisplayPort controller for handling USB Type-C orientation switching and propagating HPD signals. Extend the binding to allow these connections to be described. Tested-by:
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Vinod Koul authored
This brings in the Qcom qmp patch fixes into next as well
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Frank Li authored
Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB disconnection issue during enumeration or suspend state for difference platform. Reviewed-by:
Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-7-Frank.Li@nxp.comSigned-off-by:
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Frank Li authored
Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB disconnection issue during enumeration or suspend state for difference platform. Signed-off-by:
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Peter Chen authored
For NXP platform design, the PHY can't know VBUS well, it causes the FSM in controller seeing the disconnection at L1 use case. With .set_mode API introduced, the controller driver could force PHY seeing B Session VALID when it is at the device mode (VBUS is there), and keep FSM working well. Signed-off-by:
Peter Chen <peter.chen@nxp.com> Signed-off-by:
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Peter Chen authored
Very limited parts may fail to work on full speed mode (both host and device modes) for USB3 port due to higher threshold in full speed receiver of USB2.0 PHY. One example failure symptom is, the enumeration is failed when connecting full speed USB mouse to USB3 port, especially under high temperature. The workaround is to configure threshold voltage value of single ended receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101. Signed-off-by:
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Peter Chen authored
For USB2 L1 use cases, some hosts may start transferring less than 20us after End of Resume, it causes the host seeing corrupt packet from the device side. The reason is the delay time between PHY powers up and txvalid is 20us. To fix it, we change the delay value as 0us. Signed-off-by:
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Peter Chen authored
There is an offset for USB2PHY in SALVO phy, add offset parameter for read and write API to cover both USB2 and USB3 PHY control. Signed-off-by:
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- 17 May, 2023 2 commits
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Bhupesh Sharma authored
Add support for the new qcm2290 / sm6115 binding. The USB QMP phy on these devices supports 2 lanes. Note that the binding now does not describe every register subregion and instead the driver holds the corresponding offsets. While at it also include support for PCS_MISC region which was left out earlier. Signed-off-by:
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Bhupesh Sharma authored
'qcom,msm8996-qmp-usb3-phy.yaml' defines bindings for several PHYs which predate USB -> USB+DP migration. Since SM6115 and QCM2290 nodes for USB QMP phy are being added to dtsi files by followup patches, move these bindings instead to the newer style 'qcom,sc8280xp-qmp-usb3-uni-phy.yaml' file. Since no device trees use these bindings presently, so we have no ABI breakages with this patch. Signed-off-by:
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- 16 May, 2023 4 commits
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Siddharth Vadapalli authored
TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's SoC data. Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-3-s-vadapalli@ti.comSigned-off-by:
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Siddharth Vadapalli authored
Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by:
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Siddharth Vadapalli authored
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by:
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Siddharth Vadapalli authored
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by:
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