- 23 Jul, 2021 16 commits
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Eric Yang authored
[Why] When an riommu invalidation request come at the same time as a pipe is disabled there can be a case where DCN cannot ACK the request if only one VMID is setup in the inuse list. [How] Setup a second unused VMID will work around the issue. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nevenko Stupar authored
DCN 3x increased Line buffer size for DCHUB latency hiding, from 4 lines of 4K resolution lines to 5 lines of 4K resolution lines. All Line Buffer can be used as extended memory for P State change latency hiding. The maximum number of lines is increased to 32 lines. Finally, LB_MEMORY_CONFIG_1 (LB memory piece 1) and LB_MEMORY _CONFIG_2 (LB memory piece 2) are not affected, no change in size, only 3 pieces is affected, i.e., when all 3 pieces are used in both LB_MEMORY_CONFIG_0 and LB_MEMORY_CONFIG_3 (for 4:2:0) modes. Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Signed-off-by:
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Mikita Lipski authored
[why] DCN31 doesn't have MALL in DMUB so to avoid sending unknown commands to DMUB just remove the function pointer. [how] Remove apply_idle_power_optimizations from function pointers structure for DCN31 Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
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sunglee authored
[WHY] When finding a second pipe for pipe split, currently will look for bottom pipe in context first to decide the second pipe. This causes issues in 2 plane to 1 plane transitions like fullscreen video where bottom pipe no longer exists in the new configuration. [HOW] If previous context had an ODM pipe, use that to find the secondary pipe first before looking at bottom pipe. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
sunglee <sunglee@amd.com> Signed-off-by:
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Camille Cho authored
[Why] We used to unconditionally set backlight path as AUX for panels capable of backlight adjustment via DPCD in set default brightness. [How] This should be limited to OLED panel only since we control backlight via PWM path for SDR mode in LCD HDR panel. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Camille Cho <Camille.Cho@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why & How] We're missing a default value for dram_channel_width_bytes in the DCN3.1 SOC bounding box and we don't currently have the interface in place to query the actual value from VBIOS. Put in a hardcoded default until we have the interface in place. Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Hardcoding the VCO frequency isn't correct since we don't own or control the value. In the case where the hardcode is also missing we can't lightup display. [How] Query from the CLK register instead. Update the DFS frequency to be able to compute the VCO frequency. Reviewed-by:
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Bindu Ramamurthy authored
[Why] Initialize socclk entries in bandwidth params for dcn302, dcn303. [How] Fetch the sockclk values from smu for the DPM levels and for the DPM levels where smu returns 0, previous level values are reported. Reviewed-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Vertical and horizontal borders in timings are treated as increasing the active area - vblank and hblank actually shrink. Our input into DML does not include these borders so it incorrectly assumes it has more time than available for vstartup and tmdl calculations for some modes with borders. An example of such a timing would be 640x480@72Hz: h_total: 832 h_border_left: 8 h_addressable: 640 h_border_right: 8 h_front_porch: 16 h_sync_width: 40 v_total: 520 v_border_top: 8 v_addressable: 480 v_border_bottom: 8 v_front_porch: 1 v_sync_width: 3 pix_clk_100hz: 315000 [How] Include borders as part of destination vactive/hactive. This change DCN20+ so it has wide impact, but the destination vactive and hactive are only really used for vstartup calculation anyway. Most modes do not have vertical or horizontal borders. Reviewed-by:
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Michael Strauss authored
[WHY] Enable feature for 21.40 Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Signed-off-by:
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Aric Cyr authored
Reviewed-by:
Shahin Khayyer <Shahin.Khayyer@amd.com> Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Victor Lu authored
[why] A comparison error made it possible to not iterate through all the specified prefetch modes. [how] Correct "<" to "<=" Reviewed-by:
Yongqiang Sun <Yongqiang.Sun@amd.com> Acked-by:
Victor Lu <victorchengchi.lu@amd.com> Signed-off-by:
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Jake Wang authored
[Why] During headless boot, DIG may be on which causes HW/SW discrepancies. To avoid this we power down hardware on boot if DIG is turned on. With introduction of multiple eDP, hardware power down is being bypassed under certain conditions. [How] Fixed hardware power down bypass, and ensured hardware will power down if DIG is on and seamless boot is not enabled. Reviewed-by:
Jake Wang <haonan.wang2@amd.com> Signed-off-by:
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Wesley Chalmers authored
Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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Zhan Liu authored
[Why] Theoretically, per DP 1.4a spec, sink device needs to AUX_ACK 00340h write. However, due to hardware limitation, some sink devices have no 00340h dpcd address at all. This results in sink side fails to reply ACK, and consequently cause source side keep retrying DPCD write on DPCD 00340h. This results in significant delay when DPCD 00340h write is triggered (e.g. at S3 resume). [How] Check whether sink device could ACK on DPCD 00340h write on boot. If sink device fails to ACK, then remember that, so we won't write to DPCD 00340h later on. There will be a drm.debug KMS level message to inform user once a 00340h DPCD write is skipped on purpose. Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
Zhan Liu <zhan.liu@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Print a debug message when dcc validation fails in the display driver. Most DCC enablement related errors are from userspace. Adding a debug print in case of a failure from display driver will aid quicker triage. Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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- 21 Jul, 2021 10 commits
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Aric Cyr authored
Acked-by:
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Anthony Koo authored
- Add reserved bits for future feature development - Fix issue with mismatch with type const Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
This tends to take miliseconds in certain scenarios and we'd rather not wait that long. Due to how this interacts with det size update and locking waiting should not be necessary as compbuf updates before unlock. Add a watch for config error instead as that is something we actually do care about. Acked-by:
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Ian Chen authored
Reserve padding bytes for new feature implementation Acked-by:
Ian Chen <ian.chen@amd.com> Signed-off-by:
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Eric Yang authored
[Why] During S4/S5/reboot, sometimes riommu invalidation request arrive too early, DCN may be unable to respond to the invalidation request resulting in pstate hang. [How] VBIOS will force allow pstate for riommu invalidation and driver will clear it after powering down display pipes. Acked-by:
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Josip Pavic authored
[Why & How] Extend existing state collection functions to add some additional registers useful for debug, and add state collection function for DC hubbub Acked-by:
Josip Pavic <Josip.Pavic@amd.com> Signed-off-by:
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Mikita Lipski authored
[why] Lowering clocks when entering S2 Idle state causes DMUB to hang with Diags. [how] Do not enter S2 optimization with Diags on dcn301 to prevent DMUB hang. Acked-by:
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Oliver Logush authored
[why] The units of the time_per_pixel variable were incorrect, this had to be changed for the code to properly function. [how] The change was very straightforward, only required one line of code to be changed where the calculation was done. Acked-by:
Oliver Logush <oliver.logush@amd.com> Signed-off-by:
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Krunoslav Kovac authored
[why] The current logic checks if there's an upper pipe whose viewport completely covers the current pipe viewport. This fails in pipe splitting case as you can have layer 1 pipe that crosses the two layer 0 pipes where it's contained in both, but neither covers it completely, hence we allow the cursor on both layers. [How] Instead of trying to "sum up" rectangles from the higher level pipes which could leave gaps and would not work generically, we will assume if there's an upper layer that is active, it will control the HW cursor. Acked-by:
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Charlene Liu authored
[why] currently dc has never reset this dpcd_cap.dpcd_rev. [how] ideally we should reset this before redo detection. change the passive dongle only for now to reduce the impact. Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
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- 16 Jul, 2021 14 commits
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Liviu Dudau authored
Commit 72a7cf0a ("drm/amd/display: Keep linebuffer pixel depth at 30bpp for DCE-11.0.") doesn't seems to have fixed 10bit 4K rendering over DisplayPort for CIK GPUs. On my machine with a HAWAII GPU I get a broken image that looks like it has an effective resolution of 1920x1080 but scaled up in an irregular way. Reverting the commit or applying this patch fixes the problem on v5.14-rc1. Fixes: 72a7cf0a ("drm/amd/display: Keep linebuffer pixel depth at 30bpp for DCE-11.0.") Acked-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by:
Liviu Dudau <liviu@dudau.co.uk> Signed-off-by:
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Kevin Wang authored
1. using vram aper to access vram if possible 2. avoid MM_INDEX/MM_DATA is not working when mmio protect feature is enabled. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Kevin Wang authored
using exiting function to replace duplicate code blocks in amdgpu_ttm_vram_write(). Signed-off-by:
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Kevin Wang authored
split amdgpu_device_access_vram() 1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram 2. amdgpu_device_aper_access(): using vram aperature to access vram (option) Signed-off-by:
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Colin Ian King authored
Don't populate the const array common_rates on the stack but instead it static. Makes the object code smaller by 80 bytes: Before: text data bss dec hex filename 268019 98322 256 366597 59805 ../display/amdgpu_dm/amdgpu_dm.o After: text data bss dec hex filename 267843 98418 256 366517 597b5 ../display/amdgpu_dm/amdgpu_dm.o Reduction of 80 bytes (gcc version 10.3.0) Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Tao Zhou authored
Update the version to 0xD for beige_goby. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
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Tao Zhou authored
Update gc_10_3_4 golden setting. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Likun Gao authored
Update GFX golden setting for sienna_cichlid. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Xiaojian Du authored
This patch is to update the golden setting for vangogh. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Guchun Chen authored
For the unknown CEA parse case on DMUB-enabled ASICs, dmesg will print an error message like below, this will be captured by automation tools as it has the word like ERROR during boot up and treated as a false error, as it does not break bootup process. So use DRM_WARN printing for this. [drm:amdgpu_dm_update_freesync_caps [amdgpu]] *ERROR* Unknown EDID CEA parser results v2: Use DRM_WARN to print such info. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Add USBC PD FW implementation here to be used with relevant ASICs. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
System memory-based implementation for updating the USBCPD is deprecated for so switching to LFB based implementation for all the ASICs. Signed-off-by:
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Veerabadhran Gopalakrishnan authored
Optimized the code for codec info structure initialization Signed-off-by:
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Signed-off-by:
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Veerabadhran Gopalakrishnan authored
Added the supported codecs in the video capabilities query. Signed-off-by:
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