- 06 Dec, 2022 29 commits
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Konrad Dybcio authored
Configure regulators present on the Xperia 10 IV that are reachable via SMD RPM. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115152727.9736-9-konrad.dybcio@linaro.org
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Konrad Dybcio authored
Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on the Xperia 10 IV. Signed-off-by:
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Konrad Dybcio authored
Enable QUPs & GPI DMA on the Xperia 10 IV. Signed-off-by:
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Konrad Dybcio authored
Configure the second SDHCI bus controller, which usually the interface used for SD cards. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Konrad Dybcio authored
Add necessary nodes to support various QUP configurations. Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by:
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Konrad Dybcio authored
Add the pin setup for SPI/I2C configurations that are supported downstream. I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Acked-by:
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Konrad Dybcio authored
Add nodes for GPI DMA hosts on SM6375. Signed-off-by:
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Konrad Dybcio authored
PMK8350 is shipped on SID6 with some SoCs, for example with SM6375. Add some preprocessor logic to allow changing the SID in cases like this. While I am not in favour of adding #if's into the device tree, this is the least messy way to handle this. If one isn't specified, it will default to 0 (as it has been previously). Suggested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Konrad Dybcio authored
Add device node and required pinctrl settings (as well as a fixup for an existing one, whoops!) to support the Samsung Electronics touchscreen on Nagara devices. Signed-off-by:
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Konrad Dybcio authored
Add a device tree for the Xperia 5 IV (pdx224). It's literally the 1 IV with a smaller body, different panel, one camera lens (not sensor afaict) swapped out and no 3D iToF sensor, hence the device-specific DT is tiny. Be sure to follow the vbmeta disablement steps (detailed in pdx223 introduction commit message), otherwise your phone will not boot and will reject anything and everything with just a non-descriptive "Your device is corrupted" followed by a sad reboot. This should not be the case, as vbmeta should be plainly ignored in unlocked state, but what can we do.. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Turns out 1 IV is not the only Nagara device, reflect that in the DTS. Signed-off-by:
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Mao Jinlong authored
Add coresight components for sm8250. STM/ETM are added. Signed-off-by:
Tao Zhang <quic_taozha@quicinc.com> Signed-off-by:
Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by:
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Dzmitry Sankouski authored
New device support - Xiaomi Mi6 phone What works: - storage - usb - power regulators Signed-off-by:
Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by:
Konrad Dybcio <konra.dybcio@linaro.org> Signed-off-by:
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AngeloGioacchino Del Regno authored
This adds support for the Sony Xperia Loire/SmartLoire platform with a base configuration that is common across all of the devices that are based on this project. Also adds a base DT configuration for the Xperia X and Xperia X Compact (respectively, Suzu and Kugo) which is valid for both their RoW (single-sim), DSDS (dual-sim) and other regional variants of these two smartphones, that makes us able to boot to a UART console. Please note that, currently, the APC0/1 (cluster 0/1) vregs are set to a safe voltage in order to ensure boot stability until a proper solution for CPU DVFS scaling lands. Co-developed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
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AngeloGioacchino Del Regno authored
This commit adds device trees for MSM8956 and MSM8976 SoCs. They are *almost* identical, with minor differences, such as MSM8956 having two A72 cores less. However, there is a bug in Sony Loire bootloader that requires presence of all 8 cores in the cpu{} node, so these will not be deleted. Co-developed-by: -
AngeloGioacchino Del Regno authored
The PMI8950 features integrated peripherals like ADC, GPIO controller, MPPs and others. [luca@z3ntu.xyz: remove pm8950, style changes for 2022 standards, add wled] Signed-off-by:
AngeloGioacchino Del Regno <kholk11@gmail.com> Signed-off-by:
Luca Weiss <luca@z3ntu.xyz> Signed-off-by:
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AngeloGioacchino Del Regno authored
The PM8950 features integrated peripherals like ADC, GPIO controller, MPPs, PON keys and others. Add them to DT files that will be imported on boards having this PMIC combo (or one of them, anyways). Signed-off-by:
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Johan Hovold authored
When adding support for the DisplayPort part of the QMP PHY the binding (and devicetree parser) for the (USB) child node was simply reused and this has lead to some confusion. The third DP register region is really the DP_PHY region, not "PCS" as the binding claims, and lie at offset 0x2a00 (not 0x2c00). Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as there are for the USB part of the PHY (and in any case the Linux driver does not use them). Note that the sixth "PCS_MISC" region is not even in the binding. Fixes: 5aa0d1be ("arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode") Cc: stable@vger.kernel.org # 5.13 Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Johan Hovold authored
When adding support for the DisplayPort part of the QMP PHY the binding (and devicetree parser) for the (USB) child node was simply reused and this has lead to some confusion. The third DP register region is really the DP_PHY region, not "PCS" as the binding claims, and lie at offset 0x2a00 (not 0x2c00). Similarly, there likely are no "RX", "RX2" or "PCS_MISC" regions as there are for the USB part of the PHY (and in any case the Linux driver does not use them). Note that the sixth "PCS_MISC" region is not even in the binding. Fixes: 23737b95 ("arm64: dts: qcom: sm6350: Add USB1 nodes") Cc: stable@vger.kernel.org # 5.16 Signed-off-by:
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Johan Hovold authored
The source clock for the reference clock should not be described by the devicetree binding and instead this relationship should be modelled in the clock driver. Update the USB PHY nodes to match the fixed binding. Signed-off-by:
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Bjorn Andersson authored
Add the two bwmon instances and define votes for CPU -> LLCC and LLCC -> DDR, with bandwidth values based on the downstream DeviceTree. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Add the L3 interconnect path to all CPUs and define the bandwidth requirements for all opp entries across sc8280xp and sa8540p. The values are based on the tables reported by the hardware, distributed such that each value is the largest value, lower than the cluster frequency. Signed-off-by:
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Bjorn Andersson authored
Add a device node for the EPSS L3 frequency domain. Signed-off-by:
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Bjorn Andersson authored
Update all references to OSM or EPSS L3 compatibles, to include the generic compatible, as defined by the updated binding. Signed-off-by:
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Johan Hovold authored
Update the UFS PHY nodes to match the new binding. Signed-off-by:
Brian Masney <bmasney@redhat.com> Reviewed-by:
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Christian Marangi authored
This is not a fix on its own but more a cleanup. Phy qmp pcie driver currently have a workaround to handle pcs_misc not declared and add 0x400 offset to the pcs reg if pcs_misc is not declared. Correctly declare pcs_misc reg and reduce PCS size to the common value of 0x1f0 as done for every other qmp based pcie phy device. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Nícolas F. R. A. Prado authored
These devicetrees override a rt5682 node to use the rt5682s compatible, however, unlike rt5682, rt5682s doesn't have a VBAT supply. Remove the inexistent supply in the rt5682s nodes. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by:
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Nícolas F. R. A. Prado authored
The DBVDD and LDO1-IN supplies for rt5682 are required but are missing. They are supplied by the same power rail as AVDD. Add them. Reviewed-by:
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Bjorn Andersson authored
The first PM8540 PMIC has an available RTC block, describe this in the SA8295P ADP. Mark it as wakeup-source to allow waking the system from sleep. Signed-off-by:
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- 02 Dec, 2022 3 commits
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Johan Hovold authored
There are three UFS reference clocks on SC8280XP which are used as follows: - The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected to either controller. - The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks provide reference clocks to the two PHYs. Note that this depends on first updating the clock driver to reflect that all three clocks are sourced from CXO. Specifically, the UFS controller driver expects the device reference clock to have a valid frequency: ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0 Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Fixes: 8d6b458c ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock") Fixes: f3aa975e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy") Link: https://lore.kernel.org/lkml/Y2OEjNAPXg5BfOxH@hovoldconsulting.com/ Cc: stable@vger.kernel.org # 5.20 Signed-off-by:
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Johan Hovold authored
The devices on the SC8280XP PCIe buses are cache coherent and must be marked as such to avoid data corruption. A coherent device can, for example, end up snooping stale data from the caches instead of using data written by the CPU through the non-cacheable mapping which is used for consistent DMA buffers for non-coherent devices. Note that this is much more likely to happen since commit c44094ee ("arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()") that was added in 6.1 and which removed the cache invalidation when setting up the non-cacheable mapping. Marking the PCIe devices as coherent specifically fixes the intermittent NVMe probe failures observed on the Thinkpad X13s, which was due to corruption of the submission and completion queues. This was typically observed as corruption of the admin submission queue (with well-formed completion): could not locate request for tag 0x0 nvme nvme0: invalid id 0 completed on queue 0 or corruption of the admin or I/O completion queues (malformed completion): could not locate request for tag 0x45f nvme nvme0: invalid id 25695 completed on queue 25965 presumably as these queues are small enough to not be allocated using CMA which in turn make them more likely to be cached (e.g. due to accesses to nearby pages through the cacheable linear map). Increasing the buffer sizes to two pages to force CMA allocation also appears to make the problem go away. Fixes: 813e8315 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Bjorn Andersson authored
Mergeback arm64-fixes-for-6.1 to avoid merge conflicts.
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- 15 Nov, 2022 7 commits
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Konrad Dybcio authored
The DMA properties in this DT are identical to the ones already defined in sdm845.dtsi. Remove them. Signed-off-by:
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Konrad Dybcio authored
Wire up necessary supplies to USB PHYs to enable USB3 on Sagami and remove all the limit-to-USB2 properties. Signed-off-by:
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Konrad Dybcio authored
Configure most RPMh-controlled regulators on SoMC Sagami. The missing ones (on pm8350b and pm8008[ij]) will be configured when driver support is added. Thankfully, it looks like PDX215 and PDX214 don't have any differences when it comes to PM8350/PM8350C/PMR735a. Signed-off-by:
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Douglas Anderson authored
The 1-mic and 3-mic dtsi still had two minor cosmetic differences after commit '3d11e7e1 ("arm64: dts: qcom: sc7280: sort out the "Status" to last property with sc7280-herobrine-audio-rt5682.dtsi")'. Let's fix them so the two files diff better. This is expected to have no effect though it will slightly change the generated dtb by removing an unnecessary 'status = "okay"' from the sound node. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Krzysztof Kozlowski authored
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Suggested-by:
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Krzysztof Kozlowski authored
PCIe on MSM8996 and MSM8998 use the same clocks, so use one order to make the binding simpler. Signed-off-by:
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Krzysztof Kozlowski authored
Add new compatible for MSM8998 (compatible with MSM8996) to allow further customizing if needed and to accurately describe the hardware. Signed-off-by:
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- 12 Nov, 2022 1 commit
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Johan Hovold authored
Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to PCIe4. Signed-off-by:
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