- 11 Jun, 2015 5 commits
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Rob Clark authored
Somehow this got lost when msm atomic support was first merged. Signed-off-by:Rob Clark <robdclark@gmail.com>
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Rob Clark authored
Dump a bit more info when the GPU hangs, without having hang_debug enabled (which dumps a *lot* of registers). Also dump the scratch registers, as they are useful for determining where in the cmdstream the GPU hung (and they seem always safe to read when GPU has hung). Note that the freedreno gallium driver emits increasing counter values to SCRATCH6 (to identify tile #) and SCRATCH7 (to identify draw #), so these two in particular can be used to "triangulate" where in the cmdstream the GPU hung. Signed-off-by: -
Dan Carpenter authored
The goto is correct, and we never reach the return statement so just delete the dead code. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Dan Carpenter authored
virtio_gpu_alloc_object() returns an error pointer, it never returns NULL. Fixes: dc5698e8 ('Add virtio gpu driver.') Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
More fixes for amdgpu for 4.2. We've integrated Jerome's comments about the interface among other things. I'll be on vacation next week so Christian will be handling any updates next week. * 'drm-next-4.2-amdgpu' of git://people.freedesktop.org/~agd5f/linux: (23 commits) drm/amdgpu: fix a amdgpu_dpm=0 bug drm/amdgpu: don't enable/disable display twice on suspend/resume drm/amdgpu: fix UVD/VCE VM emulation drm/amdgpu: enable vce powergating drm/amdgpu/iceland: don't call smu_init on resume drm/amdgpu/tonga: don't call smu_init on resume drm/amdgpu/cz: don't call smu_init on resume drm/amdgpu: update to latest gfx8 golden register settings drm/amdgpu: whitespace cleanup in gmc8 golden regs drm/admgpu: move XDMA golden registers to dce code drm/amdgpu: fix the build on big endian drm/amdgpu: cleanup UAPI comments drm/amdgpu: remove AMDGPU_CTX_OP_STATE_RUNNING drm/amdgpu: remove the VI hardware semaphore in ring sync drm/amdgpu: set the gfx config properly for all CZ variants (v2) drm/amdgpu: also print the pci revision when printing the pci ids drm/amdgpu: cleanup VA IOCTL drm/amdgpu: fix saddr handling in amdgpu_vm_bo_unmap drm/amdgpu: fix amdgpu_vm_bo_map drm/amdgpu: remove unused AMDGPU_IB_FLAG_GDS ...
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- 10 Jun, 2015 14 commits
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Sonny Jiang authored
Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
We were doing it in the common code and in the IP specific code. Remove the IP specific code. The common code handles the ordering properly. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Christian König authored
Signed-off-by:
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Sonny Jiang authored
Enable VCE dpm and powergating. VCE dpm dynamically scales the VCE clocks on demand. Signed-off-by:
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Alex Deucher authored
smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by:
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Alex Deucher authored
smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by:
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Alex Deucher authored
smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by:
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Alex Deucher authored
Reviewed-by:
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Alex Deucher authored
Reviewed-by:
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Alex Deucher authored
Already moved other display registers. Reviewed-by:
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Alex Deucher authored
Some leftover copy and pastes from radeon that never got updated. Reviewed-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Christian König authored
No functional change. Signed-off-by:
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Christian König authored
Not used. Signed-off-by:
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David Zhang authored
Signed-off-by:
David Zhang <david1.zhang@amd.com> Reviewed-by:
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- 09 Jun, 2015 5 commits
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Alex Deucher authored
Need to adjust the number of CUs and RBs. v2: get proper values Reviewed-by:
Samuel Li <samuel.li@amd.com> Signed-off-by:
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Alex Deucher authored
The driver makes use of this information so print if to aid in debugging. Reviewed-by:
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Christian König authored
Remove the unnecessary returned status and make the IOCTL write only. Signed-off-by:
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Christian König authored
Signed-off-by:
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Christian König authored
We need to reset the bo_va address, otherwise new mappings wouldn't be updated in the page table. Signed-off-by:
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- 05 Jun, 2015 16 commits
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Jammy Zhou authored
Signed-off-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
amdgpu submits both kernel and user fences, but just need one interrupt, disable user fence interrupt and don't effect user fence. v2: fix merge error Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Christian König authored
Signed-off-by:
monk liu <monk.liu@amd.com>
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Jack Xiao authored
Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Dave Airlie authored
Signed-off-by: -
git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
This is the big pull request for amdgpu, the new driver for VI+ AMD asics. I currently supports Tonga, Iceland, and Carrizo and also contains a Kconfig option to build support for CI parts for testing. All major functionality is supported (displays, gfx, compute, dma, video decode/encode, etc.). Power management is working on Carrizo, but is still being worked on for Tonga and Iceland. * 'drm-next-4.2-amdgpu' of git://people.freedesktop.org/~agd5f/linux: (106 commits) drm/amdgpu: only support IBs in the buffer list (v2) drm/amdgpu: add vram_type and vram_bit_width for interface query (v2) drm/amdgpu: add ib_size/start_alignment interface query drm/amdgpu: add me/ce/pfp_feature_version interface query drm/amdgpu add ce_ram_size for interface query drm/amdgpu add max_memory_clock for interface query (v2) drm/amdgpu: add hdp flush for gfx8 compute ring drm/amdgpu: fix no hdp flush for compute ring drm/amdgpu: add HEVC/H.265 UVD support drm/amdgpu: stop loading firmware with pm.mutex locked drm/amdgpu: remove mclk_lock drm/amdgpu: fix description of vm_size module parameter (v2) drm/amdgpu: remove all sh mem register modification in vm flush drm/amdgpu: rename GEM_OP_SET_INITIAL_DOMAIN -> GEM_OP_SET_PLACEMENT drm/amdgpu: fence should be added to shared slot drm/amdgpu: sync fence of clear_invalids (v2) drm/amdgpu: max_pde_used usage should be under protect drm/amdgpu: fix bug of vm_bo_map (v2) drm/amdgpu: implement the allocation range (v3) drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2) ...
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Frediano Ziglio authored
This function could return a NULL pointer in case of handle not present and in case of out of memory conditions however caller function always returned EINVAL error hiding a possible ENOMEM. This patch change the function to return the error instead to be able to propagate the error instead of assuming EINVAL. Signed-off-by:
Frediano Ziglio <fziglio@redhat.com> Reviewed-by:
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Frediano Ziglio authored
In qxlhw_handle_to_bo we incremented counters twice, one time for release object and one for reloc_info. In the main function however reloc_info references was drop much earlier than release so keeping the pointer only on release is safe and make cleaning process easier. Signed-off-by:
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Frediano Ziglio authored
qxl_bo structure has two reference counters, one in the GEM object and another in the TTM object. The GEM object keep a counter to the TTM object so when GEM counter reached zero the TTM counter (using qxl_bo_unref) was decremented. The qxl object is fully freed (both GEM and TTM part are cleaned) when the TTM counter reach zero. One issue was that surface idr structure has no owning on qxl_bo objects however it contains a pointer to qxl_bo object. This caused some nasty race condition for instance qxl_bo object was reaped even after counter was already zero. This patch fix these races moving main counter (the one used by qxl_bo_(un)ref) to GEM object which cleanup routine (qxl_gem_object_free) remove the idr pointer (using qxl_surface_evict) when the counters are still valid. Signed-off-by:
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Frediano Ziglio authored
Enable format string checks for qxl_io_log and remove resulting warnings which could lead to memory errors on different platform or just printing wrong information. Signed-off-by:
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Frediano Ziglio authored
Free resources correctly if function fails Signed-off-by:
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Frediano Ziglio authored
This function return handle to allocated release object which is an int. Signed-off-by:
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Frediano Ziglio authored
Only EBUSY error was handled. This could cause code to believe reserve was successful while it failed. Signed-off-by:
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Frediano Ziglio authored
Is we are not able to get source bo object from handle we free destination bo object and call cleanup code however destination object was already inserted in reloc_info array (num_relocs was already incremented) so on cleanup we free destination again. Signed-off-by:
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Frediano Ziglio authored
reloc_info[i] is not still initialized in the print statement. Signed-off-by:
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Frediano Ziglio authored
If the function fails reference counter to the object is not decremented causing leaks. This is hard to spot as it happens only on very low memory situations. Signed-off-by:
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