- 25 Apr, 2019 40 commits
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Mathieu Poirier authored
Configure timestamps to be emitted at regular intervals in the trace stream to temporally correlate instructions executed on different CPUs. Signed-off-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by:
Leo Yan <leo.yan@linaro.org> Tested-by:
Robert Walker <robert.walker@arm.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Mathieu Poirier authored
Resource selector pair 0 is always implemented and reserved. As such it should not be explicitly programmed. Signed-off-by:
Suzuki K Poulose <suzuki.poulose@arm.com> Tested-by:
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Mathieu Poirier authored
Set the proper bit in the configuration register when contextID tracing has been requested by user space. That way PE_CONTEXT elements are generated by the tracers when a process is installed on a CPU. Signed-off-by:
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Mathieu Poirier authored
Add to the capabilities the ITRACE property so that ITRACE START events are generated when the PMU is switched on by the core. Signed-off-by:
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Suzuki K Poulose authored
Drop the power only if we were successful in probing the device. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Drop the power handle only if we were successful. Otherwise the AMBA bus code would do the rest. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Drop the power only when we have successfully probed. Otherwise leave it to the amba probe to do the rest. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
We drop the power before we complete the probe successfully. We are supposed to drop it only when we are successful. Also, probing the etb_buffer_length happens with the power turned up. So we don't need to do that again in the helper. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
With commit c2c72941 ("coresight: platform: Cleanup coresight connection handling"), we switched to re-using coresight_connections for the coresight_device. However, that introduced a mismatch in the alloc/free of the connections. The allocation is made using devm_*, while we use kfree() to release the memory when a device is released (even though we don't support this at the moment). Fix this by leaving it to the automatic freeing of the memory. Fixes: c2c72941 ("coresight: platform: Cleanup coresight connection handling") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Merge the drivers for the two varieties of replicators into a singel one. The dynamic replicator has programming base which can be programmed to filter the trace data. The driver detects the type based on the "base" address value of the device, which is NULL for the static device. Also, while at it, remove the now obsolete DYNAMIC_REPLICATOR config entry. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
Rename the dynamic replicator specific routines for merging with the replicator driver. Also re-arrange the probe routine to make it easier to merge. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
As a preparatory step to merge the separate drivers for static and dynamic replicators, annotate the static replicator specific details. Also refactor the probe routine to make it generic in order to merge the drivers easily. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
We fail to disable the clock in case of a failure during the probe. Clean this up. Also, we are supposed to drop the pm reference only when the probing is successful. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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Suzuki K Poulose authored
If we failed to setup the DMA mask for TMC-ETR, report the error before failing the probe. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
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YueHaibing authored
Fix sparse warnings: drivers/hwtracing/coresight/coresight-catu.c:488:35: warning: symbol 'catu_helper_ops' was not declared. Should it be static? drivers/hwtracing/coresight/coresight-catu.c:493:28: warning: symbol 'catu_ops' was not declared. Should it be static? Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Mukesh Ojha <mojha@codeaurora.org> Reviewed-by:
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Arnd Bergmann authored
Clang points out a syntax error, as the etr_catu_buf_ops structure is declared 'static' before the type is known: In file included from drivers/hwtracing/coresight/coresight-tmc-etr.c:12: drivers/hwtracing/coresight/coresight-catu.h:116:40: warning: tentative definition of variable with internal linkage has incomplete non-array type 'const struct etr_buf_operations' [-Wtentative-definition-incomplete-type] static const struct etr_buf_operations etr_catu_buf_ops; ^ drivers/hwtracing/coresight/coresight-catu.h:116:21: note: forward declaration of 'struct etr_buf_operations' static const struct etr_buf_operations etr_catu_buf_ops; This seems worth fixing in the code, so replace pointer to the empty constant structure with a NULL pointer. We need an extra NULL pointer check here, but the result should be better object code otherwise, avoiding the silly empty structure. Fixes: 434d611c ("coresight: catu: Plug in CATU as a backend for ETR buffer") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Reviewed-by:
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Hans de Goede authored
Userspace can make host function calls, called hgcm-calls through the /dev/vboxguest device. In this case we should not accept all hgcm-function-parameter-types, some are only valid for in kernel calls. This commit adds proper hgcm-function-parameter-type validation to the ioctl for doing a hgcm-call from userspace. Cc: stable@vger.kernel.org Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Todd Kjos authored
When allocating space in the target buffer for the security context, make sure the extra_buffers_size doesn't overflow. This can only happen if the given size is invalid, but an overflow can turn it into a valid size. Fail the transaction if an overflow is detected. Signed-off-by:
Todd Kjos <tkjos@google.com> Signed-off-by:
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Fuqian Huang authored
The pointer should be printed with %p or %px rather than cast to long long type and printed with %016llx. Change %x to %p to print the pointer. Signed-off-by:
Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'extcon-next-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-next Chanwoo writes: Update extcon for v5.2 Detailed description for this pull request: 1. Add new extcon-intel-mrfld.c extcon provider driver - On Intel Merrifield the Basin Cove PMIC provides a feature to detect the USB connection type. This driver utilizes the feature in order to support the USB dual role detection. 2. Update the extcon provider drivers - For extcon-intel-cht-wc.c, make charger detection co-existed with OTG host mode and enable external charger. - For intel extcon driver, add common header file (extcon-intel.h) in order to remove the duplicate definitions. - For extcon-arizonal.c, disable microphone detection on driver removal. 3. - Edit comment of extcon_unregister_notifer() to fix a build warning - Add CONFIG_ACPI dependency to Kconfig to fix a build error for extcon-axp.c * tag 'extcon-next-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon: extcon: arizona: Disable mic detect if running when driver is removed extcon: axp288: Add a depends on ACPI to the Kconfig entry extcon: mrfld: Introduce extcon driver for Basin Cove PMIC extcon: intel: Split out some definitions to a common header extcon: Fix build warning for extcon_unregister_notifier comment extcon: intel-cht-wc: Enable external charger extcon: intel-cht-wc: Make charger detection co-existed with OTG host mode
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Stephen Rothwell authored
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch aims to suppress up to 18 missing-break-in-switch false positives on some architectures. Cc: Gustavo A. R. Silva <gustavo@embeddedor.com> Cc: Kees Cook <keescook@chromium.org> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by:
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Srinivas Kandagatla authored
Many nvmem providers are not very keen on having default sysfs nvmem entry, as most of the usecases for them are inside kernel itself. And in some cases read/writes to some areas in nvmem are restricted and trapped at secure monitor level, so accessing them from userspace would result in board reboots. This patch adds new NVMEM_SYSFS Kconfig to make binary sysfs entry an optional one. This provision will give more flexibility to users. This patch also moves existing sysfs code to a new file so that its not compiled in when its not really required. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by:
Gaurav Kohli <gkohli@codeaurora.org> Tested-by:
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Yangtao Li authored
Add support for H6's SID controller. It supports 4K-bit EFUSE, bigger than before. Signed-off-by:
Yangtao Li <tiny.windzz@gmail.com> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
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Yangtao Li authored
Updates license to use SPDX-License-Identifier. Acked-by:
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Yangtao Li authored
Add a binding for H6's SID controller. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Yangtao Li authored
qfprom->sunxi-sid Acked-by:
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Anson Huang authored
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Reviewed-by:
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Anson Huang authored
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by:
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Anson Huang authored
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by:
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Jorge Ramirez-Ortiz authored
When the bit_offset in the cell is zero, the pointer to the msb will not be properly initialized (ie, will still be pointing to the first byte in the buffer). This being the case, if there are bits to clear in the msb, those will be left untouched while the mask will incorrectly clear bit positions on the first byte. This commit also makes sure that any byte unused in the cell is cleared. Signed-off-by:
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by:
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Fabrice Gasnier authored
Add nvmem_cell_read_u16() helper to ease read of an u16 value on consumer side. This is inspired by nvmem_cell_read_u32() function. This helper is useful on stm32 that has 16 bits data cells stored in non volatile memory. Signed-off-by:
Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by:
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Fabrice Gasnier authored
On STM32MP15, OTP area may be read/written by using BSEC (boot, security and OTP control). BSEC registers set is composed of various regions, among which control registers and OTP shadow registers. Secure monitor calls are involved in this process to allow (or deny) access to the full range of OTP data. This adds support for reading and writing OTP data using SMC services. Data content can be aligned on 16-bits or 8-bits. Then take care of it, since BSEC data is 32-bits wide. Signed-off-by:
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Fabrice Gasnier authored
Add a read only nvmem driver for STM32 factory-programmed memory area (on-chip non-volatile storage). Signed-off-by:
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Fabrice Gasnier authored
Add documentation for STMicroelectronics STM32 Factory-programmed read only memory area. Signed-off-by:
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Chen-Yu Tsai authored
The device tree binding already lists compatible strings for these two SoCs. They don't have the defect as seen on the H3, and the size and register layout is the same as the A64. Furthermore, the driver does not include nvmem cell definitions. Add support for these two compatible strings, re-using the config for the A64. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
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Chen-Yu Tsai authored
Originally the SID e-fuses were thought to be in big-endian format. Later sources show that they are in fact native or little-endian. The most compelling evidence is the thermal sensor calibration data, which is a set of one to three 16-bit values. In native-endian they are in 16-bit cells with increasing offsets, whereas with big-endian they are in the wrong order, and a gap with no data will show if there are one or three cells. Switch to a native endian representation for the nvmem device. For the H3, the register read-out method was already returning data in native endian. This only affects the other SoCs. Signed-off-by:
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Chen-Yu Tsai authored
The sunxi_sid driver currently uses a statically allocated nvmem_config structure that is updated at probe time. This is sub-optimal as it limits the driver to one instance, and also takes up space even if the device is not present. Modify the driver to allocate the nvmem_config structure at probe time, plugging in the desired parameters along the way. Signed-off-by:
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Chen-Yu Tsai authored
SID cells are 32-bit aligned, and a multiple of 32 bits in length. The only outlier is the thermal sensor calibration data, which is 16 bits per sensor. However a whole 64 bits is allocated for this purpose, so we could consider it conforming to the rule above. Also, the register read-out method assumes native endian, unlike the direct MMIO method, which assumes big endian. Thus no endian conversion is involved. Under these assumptions, the register read-out method can be slightly optimized. Instead of reading one word then discarding 3 bytes, read the whole word directly into the buffer. However, for reads under 4 bytes or trailing bytes, we still use a scratch buffer to extract the requested bytes. We could go one step further if .word_size was 4, but changing that would affect the sysfs interface's behavior. Signed-off-by:
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Chen-Yu Tsai authored
Since the reg_read callbacks already support arbitrary, but 4-byte aligned. offsets and lengths into the SID, there is no need for another for loop just to use it to read 1 byte at a time. Read out the whole SID block in one go. Signed-off-by:
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Lucas Stach authored
The i.MX OCOTP controller is used in numerous Freescale/NXP SoCs from the MXC family, so the strict dependency on the i.MX6 SoC is too narrow. Broaden it to cover all the MXC familiy members. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Abel Vesa <abel.vesa@nxp.com> Signed-off-by:
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