Moves bo's to TTM_PL_TT for BAR mapping, to hide tiling from user.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Commit de7b7d59 introduced tiled GART, but a linear copy is
still performed. This may result in errors on eviction, fix it by
checking tiling from memtype.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: stable@vger.kernel.org #3.10+
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

Pretty much everywhere had to make the decision which to use, so it
makes a lot more sense to just have one entrypoint decide the path
to take instead.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

When the mode is set with 16bpp on QEMU, the output gets totally broken.
The culprit is the bogus register values set for 16bpp, which was likely
copied from from a wrong place.

Addresses https://bugzilla.novell.com/show_bug.cgi?id=799216Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Cc: David Airlie <airlied@linux.ie>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

Commit 8116188f ("nouveau/acpi: hook up to the MXM method for mux
switching.") broke the build on non-x86 architectures due to the new
dependency on MXM and MXM being an x86 platform driver.

It built previously since the vga switcheroo registration routines were
zereod out on !X86.  The code was built in but unused.

This patch makes all of the DSM code depend on CONFIG_VGA_SWITCHEROO,
allowing it to build on non-x86 and shrinking the module size as well.

[rdunlap@infradead.org: fix build eror when VGA_SWITCHEROO is not enabled]
Signed-off-by: Jeff Mahoney <jeffm@suse.com>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Cc: David Airlie <airlied@linux.ie>
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

This aligns with what the userspace -mga driver does in
the same situation.
Signed-off-by: Dave Airlie <airlied@redhat.com>

Here's the vblank timestamp pull request you wanted.

I addressed the few bugs that Mario pointed out and added
the r-bs.

As it has been a while since I made the changes, I gave it a
quick spin on a few different i915 machines. Fortunately
everything still seems to be fine.

* 'drm-vbl-timestamp' of git://gitorious.org/vsyrjala/linux:
  drm/i915: Add a kludge for DSL incrementing too late and ISR not working
  drm/radeon: Move the early vblank IRQ fixup to radeon_get_crtc_scanoutpos()
  drm: Pass 'flags' from the caller to .get_scanout_position()
  drm: Fix vblank timestamping constants for interlaced modes
  drm/i915: Fix scanoutpos calculations for interlaced modes
  drm: Change {pixel,line,frame}dur_ns from s64 to int
  drm: Use crtc_clock in drm_calc_timestamping_constants()
  drm/radeon: Populate crtc_clock in radeon_atom_get_tv_timings()
  drm: Simplify the math in drm_calc_timestamping_constants()
  drm: Improve drm_calc_timestamping_constants() documentation
  drm/i915: Call drm_calc_timestamping_constants() earlier
  drm/i915: Kill hwmode save/restore
  drm: Pass the display mode to drm_calc_vbltimestamp_from_scanoutpos()
  drm: Pass the display mode to drm_calc_timestamping_constants()

Some straggling drm core patches

* 'topic/core-stuff' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/gem: Always initialize the gem object in object_init
  drm/edid: Populate picture aspect ratio for CEA modes
  drm/edid: parse the list of additional 3D modes
  drm/edid: split VIC display mode lookup into a separate function
  drm: Make the connector mode_valid() vfunc return a drm_mode_status enum

Just a single fix for sparse/smatch warnings introduced by the previous
vmwgfx-next pull.

* 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux:
  drm/vmwgfx: Fix recently introduced sparse / smatch warnings and errors

Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrant <jakob@vmware.com>

At least drm/i915 expects that the obj->dev pointer is set even in
failure paths. Specifically when the shmem initialization fails we
call i915_gem_object_free which needs to deref obj->base.dev to get at
the slab pointer in the device private structure. And the shmem
allocation can easily fail when userspace is hitting open file limits.

Doing the structure init even when the shmem file allocation fails
prevents this Oops.

This is a regression from

commit 89c8233f
Author: David Herrmann <dh.herrmann@gmail.com>
Date:   Thu Jul 11 11:56:32 2013 +0200

    drm/gem: simplify object initialization

v2: Add regression note which Chris supplied.

Testcase: igt/gem_fd_exhaustion
Reported-and-Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
References: http://lists.freedesktop.org/archives/intel-gfx/2014-January/038433.html
Cc: stable@vger.kernel.org
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Cc: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

New tree with the INFO ioctl merge fixed up.  This also adds a couple
of additional minor fixes.

A few more changes for 3.14, mostly just bug fixes.  Note that:
drm/radeon: add query to fetch the max engine clock.
will conflict with 3.13 final, but the fix is pretty obvious.

* 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux: (22 commits)
  drm/radeon: add UVD support for OLAND
  drm/radeon: fix minor typos in si_dpm.c
  drm/radeon: set the full cache bit for fences on r7xx+
  drm/radeon: fix surface sync in fence on cayman (v2)
  drm/radeon/dpm: disable mclk switching on desktop RV770
  drm/radeon: fix endian handling in radeon_atom_init_mc_reg_table
  drm/radeon: write gfx pg bases even when gfx pg is disabled
  drm/radeon: bail early from enable ss in certain cases
  drm/radeon: handle ss percentage divider properly
  drm/radeon: add query to fetch the max engine clock (v2)
  drm/radeon/dp: sleep after powering up the display
  drm/radeon/dp: use usleep_range rather than udelay
  drm/radeon/dp: bump i2c-over-aux retries to 7
  drm/radeon: disable ss on DP for DCE3.x
  drm/radeon/cik: use hw defaults for TC_CFG registers
  drm/radeon: disable dpm on BTC
  drm/radeon/cik: use WAIT_REG_MEM special op for CP HDP flush
  drm/radeon/cik: use POLL_REG_MEM special op for sDMA HDP flush
  drm/radeon: consolidate sdma hdp flushing code for CIK
  drm/radeon: consolidate cp hdp flushing code for CIK
  ...

It seems this got dropped when we merged UVD support
last year.  Add this back now.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Copy/paste typos from the ni code. Should not
have any functional change.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Needed to properly flush the read caches for fences.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

We need to set the engine bit to select the ME and
also set the full cache bit.  Should help stability
on TN and cayman.

V2: fix up surface sync in ib execute as well
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Mclk switching doesn't seem to work reliably on these
cards.  Most RV770 boards specify the same mclk for all
performance levels anyway so in most cases, this has
no affect.

Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=73067Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Need to swap the data for big endian.
Notcied by sylware in IRC.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

For consistency.  These buffers aren't used when pg is
disabled.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

If the ss percentage is 0 or we are using external ss,
just bail when enabling ss.  We disable it explicitly
earlier in the modeset already.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

It's either 100 or 1000 depending on the flags in the
table.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This is needed for reporting the max GPU engine clock
in OpenCL.  This just reports the max possible engine
clock, it does not take into account current conditions
that may limit that clock.

v2: fix query number for merge with 3.13
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Adding picture aspect ratio for CEA modes based on CEA-861D Table 3 or
CEA-861E Table 4. This is useful for filling up the detail in AVI
infoframe.

v2: Ville's review comments incorporated
Added picture aspect ratio as part of edid_cea_modes instead of DRM_MODE
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

According to the DP 1.1 spec, the sink must power
up within 1ms.  Noticed while reviewing Thierry's
drm/dp patches.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Based on common dp code proposed by Thierry Reding.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

As per the DP1.2 spec.  Noticed while reviewing
Thierry's drm/dp patches. Also bump native aux
retries to 7 for consistency.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Seems to cause problems with certain DP monitors.

Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=40699Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Use the hw power up values rather than 0.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Still unstable on some boards.

Bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=73053
https://bugzilla.kernel.org/show_bug.cgi?id=68571Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: 3.13 <stable@vger.kernel.org> # 3.13

This is the preferred flushing method on CIK.

Note, this only works on the PFP so the engine bit must be
set.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This is the preferred flushing method on CIK.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

It's used in several places so move to a common shared
function.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

It's used in several places so move to a common shared
function.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

This reverts commit 99b4f251.

Semaphores work fine after further review and testing.
Cc: 3.13 <stable@vger.kernel.org> # 3.13

Parse 2D_VIC_order_X and 3D_Structure_X from the list at the end of the
HDMI Vendor Specific Data Block.

v2: Use an offset value depending on 3D_Multi_present and add
    detail_present. (Ville Syrjälä)
v3: Make sure the list is parsed even if 3D_Structure_ALL/MASK is not
    present. (Ville Syrjälä)
    Fix one length check and remove another. (Ville Syrjälä)
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

To make it clear what exactly mode_valid() should return.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

On pre-PCH platforms ISR doesn't seem to be an actual ISR, at least as
far as display interrupts are concerned. Instead it sort of looks like
some ISR bits just directly reflect the corresponding bit from PIPESTAT.
The bit appears in the ISR only if the PIPESTAT interrupt is enabled. So
in that sense it sort of looks a bit like the south interrupt scheme on
PCH platforms. So it goes something a bit like this:
PIPESTAT.status & PIPESTAT.enable -> ISR -> IMR -> IIR -> IER -> actual
interrupt

In any case that means the intel_pipe_in_vblank_locked() doesn't actually
work for pre-PCH platforms. As a last resort, add a similar kludge as radeon
has that fixes things up if we got called from the vblank interrupt,
but the scanline counter value indicates that we're not quite there yet.
We know that the scanline counter increments at hsync but is otherwise
accurate, so we can limit the kludge to the line just prior to vblank
start, instead of the relative distance that radeon uses.

Reviewed-by: mario.kleiner.de@gmail.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

i915 doesn't need this kludge for most platforms. Although we do
appear to need something similar on certain platforms, but we can
be more accurate when we apply the adjustment since we know exactly
why the scanline counter doesn't always quite match the vblank
status.

Also the current code doesn't handle interlaced modes correctly,
and we already deal with interlaced modes in i915 code.

So let's just move the current code to radeon_get_crtc_scanoutpos()
since that's why it was added. For i915 we'll add a more finely
targeted variant.

v2: Fix vpos vs. *vpos bug (Mario)

Reviewed-by: mario.kleiner.de@gmail.com
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>