- 25 Feb, 2019 40 commits
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Jian Shen authored
For revision 0x20, VF shares the same RSS config with PF. In original codes, it always return 0 when query RSS hash key for VF. This patch fixes it by return the hash key got from PF. Fixes: 374ad291 ("net: hns3: net: hns3: Add RSS general configuration support for VF") Signed-off-by:
Jian Shen <shenjian15@huawei.com> Signed-off-by:
Peng Li <lipeng321@huawei.com> Signed-off-by:
Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Jian Shen authored
For revision 0x21, the switch of VF VLAN filter is per function. It's necessary to enable VF VLAN filter for each VF when initializing. Otherwise, VF will be able to receive broadcast packets with unknown VLAN when PF enters promisc mode. Fixes: 64d114f0 ("net: hns3: Add egress/ingress vlan filter for revision 0x21") Signed-off-by:
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Peng Li authored
This patch adds support to config depth for tx|rx ring separately by ethtool command "-G". Signed-off-by:
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Yunsheng Lin authored
The hnae3_get_bit uses hnae3_get_field, and hnae3_get_field masks the data, which is unnecessary in data path. Signed-off-by:
Yunsheng Lin <linyunsheng@huawei.com> Signed-off-by:
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Yunsheng Lin authored
hnae3_set_bit and hnae3_set_field masks the data before setting the field or bit, which is unnecessary because the data is already zero initialized. Suggested-by:
John Garry <john.garry@huawei.com> Signed-off-by:
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Yunsheng Lin authored
This patch adds unlikely hint for error handling in critical data path. Signed-off-by:
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Yunsheng Lin authored
The fill_desc ops has only one implementation, and get_rxd_bnum has not been used, so this patch removes them. Signed-off-by:
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Yunsheng Lin authored
This patch limits some variables' scope as much as possible in hns3_fill_desc. Also, only set l3_type and l4_type when necessary. Signed-off-by:
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Yunsheng Lin authored
This patch uses shift offset to avoid doing mult and div operation. Signed-off-by:
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Yunsheng Lin authored
This patch adds xps setting support for hns3 driver based on the interrupt affinity info. Signed-off-by:
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David S. Miller authored
Ido Schimmel says: ==================== mlxsw: spectrum_acl: Don't take rtnl mutex for region rehash Jiri says: During region rehash, a new region is created with a more optimized set of masks (ERPs). When transitioning to the new region, all the rules from the old region are copied one-by-one to the new region. This transition can be time consuming and currently done under RTNL lock. In order to remove RTNL lock dependency during region rehash, introduce multiple smaller locks guarding dedicated structures or parts of them. That is the vast majority of this patchset. Only patch #1 is simple cleanup and patches 12-15 are improving or introducing new selftests. ==================== Signed-off-by: -
Jiri Pirko authored
Do insertions and removal of filters during rehash in higher volumes. Signed-off-by:
Jiri Pirko <jiri@mellanox.com> Signed-off-by:
Ido Schimmel <idosch@mellanox.com> Signed-off-by:
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Jiri Pirko authored
Add checking of newly added trace. Signed-off-by:
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Jiri Pirko authored
Hit the new tracepoint once the vregion migration ends. Signed-off-by:
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Jiri Pirko authored
Track the basic codepaths of delta rehash handling, using mlxsw tracepoints. Use IPv6 addresses. Signed-off-by:
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Jiri Pirko authored
Other mutexes are taking care of proper locking for this, no longer needed to take RTNL mutex here. Signed-off-by:
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Jiri Pirko authored
No longer require RTNL lock in this code. Newly introduced mutexes take care of guarding objagg and bloom filter. There is no need to guard gen_pool_alloc()/gen_pool_free() as they are fine to be called lockless. Signed-off-by:
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Jiri Pirko authored
Relax dependency on rtnl mutex during vregion_rehash_intrvl_set(). The vregion list is protected with newly introduced mutex. Signed-off-by:
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Jiri Pirko authored
Protect objagg structures by adding a mutex to ERP code and take it during the structure manipulation. Signed-off-by:
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Jiri Pirko authored
For MR ACL profile is does not make sense to do periodical rehashes, as there is only one mask in use during the whole vregion lifetime. Therefore periodical work is scheduled but the rehash never happens. So allow to enable/disable rehash for the whole group, which is added per-profile. Disable rehashing for MR profile. Addition to the vregion list is done only in case the rehash is enable on the particular vregion. Also, the addition is moved after delayed work init to avoid schedule of uninitialized work from vregion_rehash_intrvl_set(). Symmetrically, deletion from the list is done before canceling the delayed work so it is not scheduled by vregion_rehash_intrvl_set() again. Signed-off-by:
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Jiri Pirko authored
Bloom filter is shared within multiple regions. For updates, it needs to be guarded by a separate mutex. Do that in order to not rely on RTNL mutex. Signed-off-by:
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Jiri Pirko authored
In order to remove dependency on RTNL, introduce a mutex to guard vregion structure, list of chunks and list of entries in chunks. Signed-off-by:
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Jiri Pirko authored
Refactor existing _vchunk_assoc/_vchunk_deassoc() functions into _vregion_get()/_vregion_put() to make the code simpler and prepared for vregion locking. Signed-off-by:
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Jiri Pirko authored
In order to remove RTNL lock dependency, it is needed to protect the regions list in a group. Introduce a mutex to do the job. Signed-off-by:
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Jiri Pirko authored
Make the existing group structure to contain fields needed for HW region list manipulations. Move the rest of the fields into new vgroup struct. This makes layering cleaner as the vgroup struct is on higher level than low-level group struct. Also, this makes it possible to introduce fine-grained locking. Signed-off-by:
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Jiri Pirko authored
Never used, remove it. Signed-off-by:
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David S. Miller authored
Tristram Ha says: ==================== net: dsa: microchip: add MIB counters support This series of patches is to modify the KSZ9477 DSA driver to read MIB counters periodically to avoid overflow. The MIB counters should be read only when there is link. Otherwise it is a waste of time as hardware never increases the counters. Functions are added to check the port link status so that MIB counters read call is used efficiently. v4 - Use readx_poll_timeout - Fix using mutex in a timer callback function problem - use dp->slave directly instead of checking whether it is valid - Add port_cleanup function in a separate patch - Add a mutex so that changing device variables is safe v3 - Use netif_carrier_ok instead of checking the phy device pointer v2 - Create macro similar to readx_poll_timeout to use with switch - Create ksz_port_cleanup function so that variables like on_ports and live_ports can be updated inside it v1 - Use readx_poll_timeout - Do not clear MIB counters when port is enabled - Do not advertise 1000 half-duplex mode when port is enabled - Do not use freeze function as MIB counters may miss counts ==================== Signed-off-by: -
Tristram Ha authored
Add port_cleanup function to reset some device variables when the port is disabled. Add a mutex to make sure changing those variables is thread-safe. Signed-off-by:
Tristram Ha <Tristram.Ha@microchip.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Tristram Ha authored
Remove unnecessary header include. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
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Tristram Ha authored
Get port link status to know whether to read MIB counters when the link is going down. Signed-off-by:
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Tristram Ha authored
Add background MIB counter reading support. Port MIB counters should only be read when there is link. Otherwise it is a waste of time as hardware never increases those counters. There are exceptions as some switches keep track of dropped counts no matter what. Signed-off-by:
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Tristram Ha authored
Prepare PHY for proper advertisement as sometimes the PHY in the switch has its own problems even though it may share the PHY id from regular PHY but the fixes in the PHY driver do not apply. Signed-off-by:
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David S. Miller authored
Maxime Chevallier says: ==================== net: phy: marvell10g: Add 2.5GBaseT support This series adds the missing bits necessary to fully support 2.5GBaseT in the Marvell Alaska PHYs. The main points for that support are : - Making use of the .get_features call, recently introduced by Heiner and Andrew, that allows having a fully populated list of supported modes, including 2500BaseT. - Configuring the MII to 2500BaseX when establishing a link at 2.5G - Adding a small quirk to take into account the fact that some PHYs in the family won't report the correct supported abilities The rest of the series consists of small cosmetic improvements such as using the correct helper to set a linkmode bit and adding macros for the PHY ids. We also add support for the 88E2110 PHY, which doesn't require the quirk, and support for 2500BaseT in the PPv2 driver, in order to have a fully working setup on the MacchiatoBin board. Changes since V1 : Fixed formatting issue in patch 01, rebased. ==================== Signed-off-by: -
Maxime Chevallier authored
This patch adds support for the 88x2110 PHY, which is similar to the already supported 88x3310 PHY without the SFP interface. It supports 10/100/1000BASET along with 2.5GBASET, 5GBASET and 10GBASET, with the same interface modes that are used by the 3310. This PHY don't have the same issue as the 88x3310 regarding 2.5/5G abilities, and correctly follows the 802.3bz standard to list the supported abilities. Signed-off-by:
Maxime Chevallier <maxime.chevallier@bootlin.com> Suggested-by:
Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by:
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Maxime Chevallier authored
The PPv2 controller is able to support 2.5G speeds, allowing to use 2.5GBASET in conjunction with PHYs that use 2500BASEX as their MII interface when using this mode. Signed-off-by:
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Maxime Chevallier authored
As per 802.3bz, if bit 14 of (1.11) "PMA Extended Abilities" indicates whether or not we should read register (1.21) "2.52/5G PMA Extended Abilities", which contains information on the support of 2.5GBASET and 5GBASET. After testing on several variants of PHYS of this family, it appears that bit 14 in (1.11) isn't always set when it should be. PHYs 88X3310 (on MacchiatoBin) and 88E2010 do support 2.5G and 5GBASET, but don't have 1.11.14 set. Their register 1.21 is filled with the correct values, indicating 2.5G and 5G support. PHYs 88E2110 do have their 1.11.14 bit set, as it should. Signed-off-by:
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Maxime Chevallier authored
The PHY ID corresponding to the 88X3310 is also used for other PHYs in the same family, such as the 88E2010. Use a #define for the PHY id, that ignores the last nibble. Signed-off-by:
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Maxime Chevallier authored
The Marvell Alaska family of PHYs supports 2.5GBaseT and 5GBaseT modes, as defined in the 802.3bz specification. Upon establishing a 2.5GBASET link, the PHY will reconfigure it's MII interface to 2500BASEX. At 5G, the PHY will reconfigure it's interface to 5GBASE-R, but this mode isn't supported by any MAC for now. This was tested with : - The 88X3310, which is on the MacchiatoBin - The 88E2010, an Alaska PHY that has no fiber interfaces, and is limited to 5G maximum speed. Signed-off-by:
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Maxime Chevallier authored
Cosmetic patch making use of helpers dedicated to linkmodes handling. Signed-off-by:
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Maxime Chevallier authored
The Alaska family of 10G PHYs has more abilities than the ones listed in PHY_10GBIT_FULL_FEATURES, the exact list depending on the model. Make use of the newly introduced .get_features call to build this list, using genphy_c45_pma_read_abilities to build the list of supported linkmodes, and adding autoneg ability based on what's reported by the AN MMD. .config_init is still used to validate the interface_mode. Signed-off-by:
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