- 04 Oct, 2022 7 commits
-
-
Stephen Boyd authored
- Add resets for MediaTek MT8195 PCIe and USB - Remove DaVinci DM644x and DM646x clk driver support * clk-samsung: clk: samsung: MAINTAINERS: add Krzysztof Kozlowski clk: samsung: exynos850: Implement CMU_MFCMSCL domain clk: samsung: exynos850: Implement CMU_IS domain clk: samsung: exynos850: Implement CMU_AUD domain clk: samsung: exynos850: Style fixes clk: samsung: exynosautov9: add fsys1 clock support clk: samsung: exynosautov9: add fsys0 clock support clk: samsung: exynosautov9: correct register offsets of peric0/c1 clk: samsung: exynosautov9: add missing gate clks for peric0/c1 dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL dt-bindings: clock: exynos850: Add Exynos850 CMU_IS dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add fys0 clock definitions clk: samsung: exynos7885: Add TREX clocks clk: samsung: exynos7885: Implement CMU_FSYS domain dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 clk: samsung: exynos-clkout: Use of_device_get_match_data() * clk-mtk: (42 commits) clk: mediatek: add driver for MT8365 SoC clk: mediatek: Export required common code symbols clk: mediatek: Provide mtk_devm_alloc_clk_data dt-bindings: clock: mediatek: add bindings for MT8365 SoC clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks ... * clk-rm: clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x * clk-ast: clk: ast2600: BCLK comes from EPLL * clk-qcom: (97 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks ...
-
Stephen Boyd authored
Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'clk-xilinx' into clk-next - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging * clk-ofnode: clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: tegra20: Fix refcount leak in tegra20_clock_init clk: tegra: Fix refcount leak in tegra114_clock_init clk: tegra: Fix refcount leak in tegra210_clock_init clk: sprd: Hold reference returned by of_get_parent() clk: berlin: Add of_node_put() for of_get_parent() clk: at91: dt-compat: Hold reference returned by of_get_parent() clk: qoriq: Hold reference returned by of_get_parent() clk: oxnas: Hold reference returned by of_get_parent() clk: st: Hold reference returned by of_get_parent() clk: tegra: Add missing of_node_put() clk: meson: Hold reference returned by of_get_parent() clk: nomadik: Add missing of_node_put() * clk-bindings: dt-bindings: clock: drop minItems equal to maxItems dt-bindings: clock: gpio-gate-clock: Convert to json-schema dt-bindings: clock: Move versaclock.h to dt-bindings/clock dt-bindings: clock: Move lochnagar.h to dt-bindings/clock * clk-cleanup: clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: nxp: fix typo in comment clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clkdev: Simplify devm_clk_hw_register_clkdev() function clkdev: Remove never used devm_clk_release_clkdev() clk: Remove never used devm_of_clk_del_provider() clk: pistachio: Fix initconst confusion clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data clk: do not initialize ret clk: remove extra empty line clk: Fix comment typo clk: move from strlcpy with unused retval to strscpy * clk-zynq: clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate clk: zynqmp: Check the return type zynqmp_pm_query_data clk: zynqmp: Add a check for NULL pointer clk: zynqmp: Replaced strncpy() with strscpy() clk: zynqmp: Fix stack-out-of-bounds in strncpy` clk: zynqmp: make bestdiv unsigned * clk-xilinx: clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: clocking-wizard: Update the compatible clk: clocking-wizard: Fix the reconfig for 5.2 clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs clk: clocking-wizard: Move clocking-wizard out dt-bindings: add documentation of xilinx clocking wizard
-
Stephen Boyd authored
This PLL frequency needs a UL postfix to avoid compiler warnings on 32-bit architectures. Fixes: 184fdd87 ("clk: qcom: Add global clock controller driver for SM6375") Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
-
Konrad Dybcio authored
gcc_parent_data_15 and gcc_parent_map_15 are not used in this driver. Remove them. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20221003211438.25691-1-konrad.dybcio@somainline.org Fixes: 184fdd87 ("clk: qcom: Add global clock controller driver for SM6375") Signed-off-by:
-
Christian Marangi authored
Convert the driver to parent data API. From the Documentation pll8_vote and pxo should be declared in the DTS so fw_name can be used instead of parent_names. .name is changed to the legacy pxo_board following how it's declared in other drivers. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220914144743.17369-2-ansuelsmth@gmail.comReviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
-
Christian Marangi authored
Introduce (devm_)hw_register_mux_parent_data_table new API. We have basic support for clk_register_mux using parent_data but we lack any API to provide a custom parent_map. Add these 2 new API to correctly handle these special configuration instead of using the generic __(devm_)clk_hw_register_mux API. Signed-off-by:
-
Stephen Boyd authored
Merge tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: This introduces display clock controllers are introduces for SM6115 and SM8450, and SC8280XP gains a GPU clock controller. MSM8909 and SM6375 gains global and SMD RPM clock controller drivers. The handling of GDSCs with PWRSTS_RET was fixed, to keep the GDSC on while powering down the parent supply. This solved retention issues during suspend of USB on sc7180/7280 and SC8280XP. SM6115 and QCM2260 are moved to reuse PLL configuration. SDM660 SDCC1 was moved to floor ops. Support for the APCS PLLs for IPQ8064, IPQ8074 and IPQ6018 was added/fixed. The MSM8996 CPU clocks was updated, with support for ACD clocks added. Support for SDM670 was added to the SDM845 Glbal clock controller and the RPMh clock controller driver. Transition to parent_data, parent_hws and use of ARRAY_SIZE() for num_parents was done for MSM8660, MSM8916, MSM8939, MSM8960 global clock controllers, IPQ8064 LPASS clock controller and MSM8960 multimedia clock controller. Support for per-reset defined delay of was introduced. * tag 'qcom-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (93 commits) clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOG dt-bindings: clock: qcom,rpmcc: Add compatible for SM6375 clk: qcom: rpmhcc: add sdm670 clocks dt-bindings: clock: add rpmhcc bindings for sdm670 ...
-
- 03 Oct, 2022 6 commits
-
-
Clément Léger authored
Set the COMMON_CLK_LAN966X option as a tristate and switch from builtin_platform_driver() to module_platform_driver() to allow building and using this driver as a module. Signed-off-by:
Clément Léger <clement.leger@bootlin.com> Link: https://lore.kernel.org/r/20220617103306.489466-1-clement.leger@bootlin.comSigned-off-by:
-
Yihao Han authored
Replace `if (!pclk->param.csr_reg)` with `else` for simplification and add curly brackets according to the kernel coding style: "Do not unnecessarily use braces where a single statement will do." ... "This does not apply if only one branch of a conditional statement is a single statement; in the latter case use braces in both branches" Please refer to: https://www.kernel.org/doc/html/v5.17-rc8/process/coding-style.htmlSigned-off-by:
Yihao Han <hanyihao@vivo.com> Link: https://lore.kernel.org/r/20220408130617.14963-1-hanyihao@vivo.comSigned-off-by:
-
Joel Stanley authored
This correction was made in the u-boot SDK recently. There are no in-tree users of this clock so the impact is minimal. Fixes: d3d04f6c ("clk: Add support for AST2600 SoC") Link: https://github.com/AspeedTech-BMC/u-boot/commit/8ad54a5ae15f27fea5e894cc2539a20d90019717Signed-off-by:
Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20220421040426.171256-1-joel@jms.id.auSigned-off-by:
-
Stephen Boyd authored
This driver uses devm_platform_ioremap_resource() and thus depends on HAS_IOMEM. Add the Kconfig dependency to avoid build issues. Reported-by:
kernel test robot <lkp@intel.com> Cc: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Fixes: c822490f ("clk: clocking-wizard: Move clocking-wizard out") Link: https://lore.kernel.org/r/20221003202608.2611295-1-sboyd@kernel.orgSigned-off-by:
-
Yang Yingliang authored
dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER. Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220913031442.980720-1-yangyingliang@huawei.comSigned-off-by:
-
Julia Lawall authored
Spelling mistake (triple letters) in comment. Detected with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/20220521111145.81697-42-Julia.Lawall@inria.frAcked-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
-
- 01 Oct, 2022 3 commits
-
-
ye xingchen authored
Return the value of_clk_add_hw_provider() directly instead of storing it in another redundant variable. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220906072322.337253-1-ye.xingchen@zte.com.cnSigned-off-by:
-
Miaoqian Lin authored
pm_runtime_get_sync() will increment pm usage counter. Forgetting to putting operation will result in reference leak. Add missing pm_runtime_put_sync in some error paths. Fixes: 9ac33b0c ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220602030838.52057-1-linmq006@gmail.comReviewed-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
-
Liang He authored
In ti_find_clock_provider(), of_find_node_by_name() will call of_node_put() for the 'from' argument, possibly putting the node one too many times. Let's maintain the of_node_get() from the previous search and only put when we're exiting the function early. This should avoid a misbalanced reference count on the node. Fixes: 51f661ef ("clk: ti: Add ti_find_clock_provider() to use clock-output-names") Signed-off-by:
Liang He <windhl@126.com> Link: https://lore.kernel.org/r/20220915031121.4003589-1-windhl@126.com [sboyd@kernel.org: Rewrite commit text, maintain reference instead of get again] Signed-off-by:
-
- 30 Sep, 2022 8 commits
-
-
Fabien Parent authored
Add clock drivers for MT8365 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Signed-off-by:
Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.comReported-by:
-
Markus Schneider-Pargmann authored
To make clk-mt8365 compilable as a module there are a few function symbols missing. This patch adds the required EXPORT_SYMBOL_GPL to the functions. Signed-off-by:
-
Markus Schneider-Pargmann authored
Provide a helper that replaces the kzalloc with devm_kzalloc so error handling gets easier. Signed-off-by:
-
Fabien Parent authored
Add the clock bindings for the MediaTek MT8365 SoC. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
-
Andy Shevchenko authored
Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220623115719.52683-3-andriy.shevchenko@linux.intel.comSigned-off-by:
-
Andy Shevchenko authored
For the entire history of the devm_clk_release_clkdev() existence (since 2018) it was never used. Remove it for good. Signed-off-by:
-
Andy Shevchenko authored
For the entire history of the devm_of_clk_del_provider) existence (since 2017) it was never used. Remove it for good. Signed-off-by:
-
Stephen Boyd authored
Merge tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux into clk-mtk Pull MediaTek clk driver updates from Chen-Yu Tsai: A lot of clean up work, as well as new drivers and new functions - New clock drivers for MediaTek Helio X10 MT6795 - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion - Shrink MT8192 clock driver by deduplicating clock parent lists * tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux: (31 commits) clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks clk: mediatek: mt8192: add mtk_clk_simple_remove clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driver clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driver clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driver ...
-
- 29 Sep, 2022 16 commits
-
-
Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928145609.375860-4-dmitry.baryshkov@linaro.org
-
Dmitry Baryshkov authored
Use parent_hws instead of hanving parent_data with just a single .hw entry to speed up and simplify parent lookups. Signed-off-by:
-
Dmitry Baryshkov authored
The MSM8939 GCC bindings are fully comptible with MSM8916, the clock controller requires the same parent clocks, move MSM8939 GCC compatible to qcom,msm8916.yaml Signed-off-by:
-
Luca Weiss authored
The USB controllers on sm6350 do not retain the state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Fix this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. Cc: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Signed-off-by:
-
Johan Hovold authored
Since commit d3997239 ("clk: qcom: gdsc: Fix the handling of PWRSTS_RET support) retention mode can be used on sc8280xp to maintain state during suspend instead of leaving the domain always on. This is needed to eventually allow the parent CX domain to be powered down during suspend. Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
-
Johan Hovold authored
Since commit 7eb231c3 ("PM / Domains: Convert pm_genpd_init() to return an error code") pm_genpd_init() can return an error which the caller must handle. The current error handling was also incomplete as the runtime PM and regulator use counts were not balanced in all error paths. Add the missing error handling to the GDSC initialisation to avoid continuing as if nothing happened on errors. Signed-off-by:
-
Chen-Yu Tsai authored
Some groups of clocks of the same type share the same list of parents. These lists were declared separately for each clock in older drivers, bloating the code. Merge some obvious duplicate parent clock lists in the MT8192 clock driver together to reduce the code size. These include: - apll_i2s*_m_parents into one as apll_i2s_m_parents - img1_parents & img2_parents into one as img_parents - msdc30_*_parents into one as msdc30_parents - camtg*_parents into cam_tg_parents - seninf*_parents into seninf_parents Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220926102523.2367530-6-wenst@chromium.orgSigned-off-by:
Chen-Yu Tsai <wenst@chromium.org>
-
Chen-Yu Tsai authored
During the previous |struct clk| to |struct clk_hw| clk provider API migration in commit 6f691a58 ("clk: mediatek: Switch to clk_hw provider APIs"), a few clk_unregister_*() calls were missed. Migrate the remaining ones to the |struct clk_hw| provider API, i.e. change clk_unregister_*() to clk_hw_unregister_*(). Fixes: 6f691a58 ("clk: mediatek: Switch to clk_hw provider APIs") Reviewed-by:
-
Chen-Yu Tsai authored
When the cleanup paths for the various clk register APIs in the MediaTek clk library were added, the one in the dividers type used the wrong type of unregister function. This would result in incorrect dereferencing of the clk pointer and freeing of invalid pointers. Fix this by switching to the correct type of clk unregistration call. Fixes: 3c3ba2ab ("clk: mediatek: mtk: Implement error handling in register APIs") Reviewed-by:
-
AngeloGioacchino Del Regno authored
Following the changes that were done for mt8183, add a clock notifier for the GPU PLL selector mux: this allows safe clock rate changes by temporarily reparenting the GPU to a safe clock (clk26m) while the MFGPLL is reprogrammed and stabilizes. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Following what was done on MT8183 and MT8195, also propagate the rate changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS. Signed-off-by:
-
AngeloGioacchino Del Regno authored
These PLLs are conflicting with GPU rates that can be generated by the GPU-dedicated MFGPLL and would require a special clock handler to be used, for very little and ignorable power consumption benefits. Also, we're in any case unable to set the rate of these PLLs to something else that is sensible for this task, so simply drop them: this will make the GPU to be clocked exclusively from MFGPLL for "fast" rates, while still achieving the right "safe" rate during PLL frequency locking. Signed-off-by:
-
AngeloGioacchino Del Regno authored
Following the changes done to MT8183, register a similar notifier for MT8195 as well, allowing safe clockrate updates for the MFGPLL. Signed-off-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220927101128.44758-8-angelogioacchino.delregno@collabora.comSigned-off-by:
-
AngeloGioacchino Del Regno authored
This clock was being registered as clk-composite through the helpers for the same in the MediaTek clock APIs but, in reality, this isn't a composite clock. Appropriately register this clock with devm_clk_hw_register_mux(). No functional changes. Signed-off-by:
-
AngeloGioacchino Del Regno authored
The MFG_BG3D is a gate to enable/disable clock output to the GPU, but the actual output is decided by multiple muxes; in particular: mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and "fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the 26MHz clock and various system PLLs. The clock gate comes after all the muxes, so its parent is mfg_ck_fast_reg, not top_mfg_core_tmp. Reparent MFG_BG3D to the latter to match the hardware and add the CLK_SET_RATE_PARENT flag to it: this way we ensure propagating rate changes that are requested on MFG_BG3D along its entire clock tree. Fixes: 35016f10 ("clk: mediatek: Add MT8195 mfgcfg clock support") Signed-off-by:
-
Chen-Yu Tsai authored
When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by:
-
