- 08 Mar, 2022 13 commits
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Ansuel Smith authored
Use ARRAY_SIZE for num_parents instead of hardcoding the value. Signed-off-by:
Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Tested-by:
Jonathan McDowell <noodles@earth.li> Signed-off-by:
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Ansuel Smith authored
Convert parent_names to parent_data to modernize the driver. Where possible use parent_hws directly. Signed-off-by:
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Ansuel Smith authored
Parent gcc_pxo_pll8_pll0 had the parent definition and parent map swapped. Fix this naming error. Signed-off-by:
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Ansuel Smith authored
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source clocks. The gcc node is also used by the tsens driver, already documented, to get the calib nvmem cells and the base reg from gcc. Use qcom,gcc.yaml as a template and remove the compatible from generic qcom,gcc-other.yaml Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Ansuel Smith authored
Simplify qcon,gcc-apq8064 Documentation by using qcom,gcc.yaml as a template and remove the compatible from qcom,gcc.yaml Signed-off-by:
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Ansuel Smith authored
Split qcom,gcc.yaml to common and specific schema to use it as a template for schema that needs to use the gcc bindings and require to add additional bindings. Signed-off-by:
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Rohit Agarwal authored
Update APCS Kconfig to reflect support for SDX65 APCS clock controller. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Rohit Agarwal authored
Update A7 PLL Kconfig to reflect support for SDX65. Signed-off-by:
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Rohit Agarwal authored
Add information for Cortex A7 PLL clock in Qualcomm platform SDX65. Signed-off-by:
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Konrad Dybcio authored
Add support for the GPU clock controller found on SM6350. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6350 SoCs. Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Add support for the display clock controller found on SM6350. Signed-off-by:
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Konrad Dybcio authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by:
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- 25 Feb, 2022 2 commits
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Bjorn Andersson authored
The Qualcomm SC8280XP platform exposes 5 clocks through the RPMh clock controller. Add these, and the relates active-only variants, to the RPMh clock controller driver. Signed-off-by:
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Bjorn Andersson authored
The Qualcomm SC8280XP has a RPMh clock controller, so add a compatible for this to the binding. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220223044516.3776637-1-bjorn.andersson@linaro.org
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- 24 Feb, 2022 3 commits
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Dirk Buchwalder authored
Use floor ops on SDCC1 APPS clock in order to round down selected clock frequency and avoid overclocking SD/eMMC cards. For example, currently HS200 cards were failling tuning as they were actually being clocked at 384MHz instead of 192MHz. This caused some boards to disable 1.8V I/O and force the eMMC into the standard HS mode (50MHz) and that appeared to work despite the eMMC being overclocked to 96Mhz in that case. There was a previous commit to use floor ops on SDCC clocks, but it looks to have only covered SDCC2 clock. Fixes: 9607f622 ("clk: qcom: ipq8074: add PCIE, USB and SDCC clocks") Signed-off-by:
Dirk Buchwalder <buchwalder@posteo.de> Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Dmitry Baryshkov authored
The driver can parse bi-tcxo clock from the clocks passed in the device tree. Specify it in schema. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Dmitry Baryshkov authored
Convert clock/qcom,camcc.txt to clock/qcom,sdm845-camcc.yaml. Signed-off-by:
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- 11 Feb, 2022 18 commits
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Bartosz Dudziak authored
Modify the existing MSM8974 multimedia clock controller driver to support the MMCC found on MSM8226 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by:
Bartosz Dudziak <bartosz.dudziak@snejp.pl> Signed-off-by:
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Bartosz Dudziak authored
Document the multimedia clock controller found on MSM8226. Signed-off-by:
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Dmitry Baryshkov authored
The "xo" fixed_factor clock is a leftover/hack from a time when we couldn't make rpmhcc the root of all clocks. It is going to be removed once all users of this clock are converted to use clocks specified through the DTS. Replace internal usage of the xo clock with the cxo (RPM_SMD_BB_CLK1) parent, specifying xo_board as a fallback. Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by:
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Dmitry Baryshkov authored
Move clock parent tables down, after the GPLL declrataions, so that we can use gpll hw clock fields in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
In preparation of updating the msm8996 gcc driver, drop all unsupported GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3). Downstream kernel also does not provide support for these GPLL sources, so it is safe to drop them. Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by:
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Dmitry Baryshkov authored
Convert the clock driver to specify parent hws/data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Signed-off-by:
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Dmitry Baryshkov authored
Move clock parent tables down, after the PLL declrataions, so that we can use pll hw clock fields in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by:
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Dmitry Baryshkov authored
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by:
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Dmitry Baryshkov authored
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data easy and errorproof. Signed-off-by:
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Dmitry Baryshkov authored
If all parents are specified as clk_hw, we can use parent_hws instead of parent_data. Signed-off-by:
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Dmitry Baryshkov authored
The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Signed-off-by:
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Dmitry Baryshkov authored
Two clocks are still using parent_names, use parent_hws instead. Signed-off-by:
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- 10 Feb, 2022 3 commits
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Loic Poulain authored
Add support for the display clock controller found in QCM2290 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). It's a porting of dispcc-scuba GPL-2.0 driver from CAF msm-4.19 kernel: https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/clk/qcom/dispcc-scuba.c?h=LE.UM.4.4.1.r3 Global clock name references (parent_names) have been replaced by parent_data and parent_hws. Clocks marked enable_safe_config have their clk_rcg2_ops moved to clk_rcg2_shared_ops. Signed-off-by:
Loic Poulain <loic.poulain@linaro.org> Signed-off-by:
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Loic Poulain authored
Add device tree bindings for display clock controller on QCM2290 SoCs. Signed-off-by:
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Robert Marko authored
Fix PCI-E clock related kernel oops that are caused by a missing clock parent. pcie0_rchng_clk_src has num_parents set to 2 but only one parent is actually set via parent_hws, it should also have "XO" defined. This will cause the kernel to panic on a NULL pointer in clk_core_get_parent_by_index(). So, to fix this utilize clk_parent_data to provide gcc_xo_gpll0 parent data. Since there is already an existing static const char * const gcc_xo_gpll0[] used to provide the same parents via parent_names convert those users to clk_parent_data as well. Without this earlycon is needed to even catch the OOPS as it will reset the board before serial is initialized with the following: [ 0.232279] Unable to handle kernel paging request at virtual address 0000a00000000000 [ 0.232322] Mem abort info: [ 0.239094] ESR = 0x96000004 [ 0.241778] EC = 0x25: DABT (current EL), IL = 32 bits [ 0.244908] SET = 0, FnV = 0 [ 0.250377] EA = 0, S1PTW = 0 [ 0.253236] FSC = 0x04: level 0 translation fault [ 0.256277] Data abort info: [ 0.261141] ISV = 0, ISS = 0x00000004 [ 0.264262] CM = 0, WnR = 0 [ 0.267820] [0000a00000000000] address between user and kernel address ranges [ 0.270954] Internal error: Oops: 96000004 [#1] SMP [ 0.278067] Modules linked in: [ 0.282751] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.10 #0 [ 0.285882] Hardware name: Xiaomi AX3600 (DT) [ 0.292043] pstate: 20400005 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.296299] pc : clk_core_get_parent_by_index+0x68/0xec [ 0.303067] lr : __clk_register+0x1d8/0x820 [ 0.308273] sp : ffffffc01111b7d0 [ 0.312438] x29: ffffffc01111b7d0 x28: 0000000000000000 x27: 0000000000000040 [ 0.315919] x26: 0000000000000002 x25: 0000000000000000 x24: ffffff8000308800 [ 0.323037] x23: ffffff8000308850 x22: ffffff8000308880 x21: ffffff8000308828 [ 0.330155] x20: 0000000000000028 x19: ffffff8000309700 x18: 0000000000000020 [ 0.337272] x17: 000000005cc86990 x16: 0000000000000004 x15: ffffff80001d9d0a [ 0.344391] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000006 [ 0.351508] x11: 0000000000000003 x10: 0101010101010101 x9 : 0000000000000000 [ 0.358626] x8 : 7f7f7f7f7f7f7f7f x7 : 6468626f5e626266 x6 : 17000a3a403c1b06 [ 0.365744] x5 : 061b3c403a0a0017 x4 : 0000000000000000 x3 : 0000000000000001 [ 0.372863] x2 : 0000a00000000000 x1 : 0000000000000001 x0 : ffffff8000309700 [ 0.379982] Call trace: [ 0.387091] clk_core_get_parent_by_index+0x68/0xec [ 0.389351] __clk_register+0x1d8/0x820 [ 0.394210] devm_clk_hw_register+0x5c/0xe0 [ 0.398030] devm_clk_register_regmap+0x44/0x8c [ 0.402198] qcom_cc_really_probe+0x17c/0x1d0 [ 0.406711] qcom_cc_probe+0x34/0x44 [ 0.411224] gcc_ipq8074_probe+0x18/0x30 [ 0.414869] platform_probe+0x68/0xe0 [ 0.418776] really_probe.part.0+0x9c/0x30c [ 0.422336] __driver_probe_device+0x98/0x144 [ 0.426329] driver_probe_device+0x44/0x11c [ 0.430842] __device_attach_driver+0xb4/0x120 [ 0.434836] bus_for_each_drv+0x68/0xb0 [ 0.439349] __device_attach+0xb0/0x170 [ 0.443081] device_initial_probe+0x14/0x20 [ 0.446901] bus_probe_device+0x9c/0xa4 [ 0.451067] device_add+0x35c/0x834 [ 0.454886] of_device_add+0x54/0x64 [ 0.458360] of_platform_device_create_pdata+0xc0/0x100 [ 0.462181] of_platform_bus_create+0x114/0x370 [ 0.467128] of_platform_bus_create+0x15c/0x370 [ 0.471641] of_platform_populate+0x50/0xcc [ 0.476155] of_platform_default_populate_init+0xa8/0xc8 [ 0.480324] do_one_initcall+0x50/0x1b0 [ 0.485877] kernel_init_freeable+0x234/0x29c [ 0.489436] kernel_init+0x24/0x120 [ 0.493948] ret_from_fork+0x10/0x20 [ 0.497253] Code: d50323bf d65f03c0 f94002a2 b4000302 (f9400042) [ 0.501079] ---[ end trace 4ca7e1129da2abce ]--- Fixes: f0cfcf1a ("clk: qcom: ipq8074: Add missing clocks for pcie") Signed-off-by:
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- 23 Jan, 2022 1 commit
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Linus Torvalds authored
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