- 26 Apr, 2022 13 commits
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Zhenneng Li authored
Signed-off-by:
Zhenneng Li <lizhenneng@kylinos.cn> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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David Zhang authored
[Why] Allow for PSR SMU optimization and PSR multiple display optimization. [How] Add feature flags of PSR smu optimization and PSR multiple display optimiztaion, and set them during init sequence. By default, flags are disabled. Signed-off-by:
David Zhang <dingchen.zhang@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Prike Liang authored
Without MMHUB clock gating being enabled then MMHUB will not disconnect from DF and will result in DF C-state entry can't be accessed during S2idle suspend, and eventually s0ix entry will be blocked. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Acked-by:
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Guo Zhengkui authored
Fix the following coccicheck warning: drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c:98:8-10: WARNING: possible condition with no effect (if == else) Reviewed-by:
Zhan Liu <zhan.liu@amd.com> Signed-off-by:
Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by:
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Alex Deucher authored
It's not used outside of dcn31_clk_mgr.c. Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
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Haohui Mai authored
The gfx_v10_0_ring_test_ib() function uses 20 bytes instead of 16 bytes during the test. The patch sets the size of the allocation to be 4-byte larger to match the actual usage. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Haohui Mai <ricetons@gmail.com> Signed-off-by:
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Haohui Mai authored
Updated the patch for the pre-vega hardware. I kept the clamping code to be safe. Reviewed-by:
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Haohui Mai authored
This patch fixes the issue where the driver miscomputes the 64-bit values of the wptr of the SDMA doorbell when initializing the hardware. SDMA engines v4 and later on have full 64-bit registers for wptr thus they should be set properly. Older generation hardwares like CIK / SI have only 16 / 20 / 24bits for the WPTR, where the calls of lower_32_bits() will be removed in a following patch. Reviewed-by:
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Tom Rix authored
Sparse reports these issues si_dpm.c:332:26: warning: symbol 'cac_weights_pitcairn' was not declared. Should it be static? si_dpm.c:1088:26: warning: symbol 'cac_weights_oland' was not declared. Should it be static? Both of these variables are only used in si_dpm.c. Single file variables should be static, so change their storage-class specifiers to static. Signed-off-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Tom Rix authored
Sparse reports these issues cik_blit_shaders.c:31:11: warning: symbol 'cik_default_state' was not declared. Should it be static? cik_blit_shaders.c:246:11: warning: symbol 'cik_default_size' was not declared. Should it be static? cik_default_state and cik_default_size are only used in cik.c. Single file symbols should be static. So move their definitions to cik_blit_shaders.h and change their storage-class-specifier to static. Remove unneeded cik_blit_shader.c Signed-off-by:
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Randy Dunlap authored
Fix kernel-doc warnings for a comment that should not use kernel-doc notation: dmub_psr.c:235: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Set PSR power optimization flags. dmub_psr.c:235: warning: missing initial short description on line: * Set PSR power optimization flags. Fixes: e5dfcd27 ("drm/amd/display: dc_link_set_psr_allow_active refactoring") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Reported-by:
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Philip Yang authored
Change SVM range mapping flags or access attributes don't trigger migration, if range is already mapped on GPUs we should update GPU mapping and pass flush_tlb flag true to amdgpu vm. Change SVM range preferred_loc or migration granularity don't need update GPU mapping, skip the validate_and_map. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Philip Yang authored
To avoid unnecessary unmap SVM range from GPUs if range is not mapped on GPUs when migrating the range. This flag will also be used to flush TLB when updating the existing mapping on GPUs. It is protected by prange->migrate_mutex and mmap read lock in MMU notifier callback. Signed-off-by:
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- 25 Apr, 2022 15 commits
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Aric Cyr authored
This version brings along following fixes: - Keep tracking of DSC packed PPS for future use - Maintain current link settings in link loss interrupt - Remove DDC write and read size check - Read PSR-SU cap DPCD for specific panel - Don't pass HostVM by default on DCN3.1 - Reset cached PSR parameters after hibernate - Add audio readback registers - Update dcn315 clk table read Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Ilya Bakoulin authored
[Why] Store current packed PPS data in dc_stream_state for future use. Reviewed-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by:
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Dillon Varone authored
Integer no longer needed. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Gary Li authored
[Why] DP compliance test case 400.3.2.3 is failed because in link loss interrupt the current link settings is not used in the DP link training. [How] In link loss interrupt, use the current link settings in the following DP link training. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
Gary Li <garyli12@amd.com> Tested-by:
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Leo Ma authored
[Why] Customer found I2C over AUX using ADL_Display_DDCBlockAccess_Get will fail when sending more than 256 bytes of data; [How] Remove the write and read size checking to allow sending data more than 256 bytes; Reviewed-by:
Leo Ma <hanghong.ma@amd.com> Tested-by:
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David Zhang authored
[why & how] For some specific eDP panel, we'd check the PSR-SU cap during boot by reading the vendor specific DPCD, otherwise it will cause to false report the eDP panel which supports PSR-SU as an non-PSR-SU panel. - add the vendor specific DPCD address in ddc_service_types header - if specific eDP panel detected, check vendor specific DPCD for PSR-SU cap Reviewed-by:
Aurabindo Jayamohanan Pillai <Aurabindo.Pillai@amd.com> Acked-by:
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Michael Strauss authored
[WHY] Roll back previous change to stop passing this value by default, instead add a debug flag to override to previous behaviour (or force HostVM calcs) Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Evgenii Krasnikov authored
[WHY] After hibernate system might be using old invalid psr_power_opt and psr_allow_active that never get reset [HOW] Reset cached Panel Self Refresh parameters when PSR is first configured for eDP in dc_link_setup_psr. Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Acked-by:
Evgenii Krasnikov <Evgenii.Krasnikov@amd.com> Tested-by:
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Ilya Bakoulin authored
[Why] Can be useful for verifying the correctness of audio output. Reviewed-by:
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Dmytro Laktyushkin authored
Clean up the sequence by making sure clk_mgr always builds a reasonable clock table regardless of what we read from smu by moving all defaults from resource soc struct to clk_mgr. Now the only thing resource soc update does is read the clock table and apply any DC specific policy decisions to how clocks are populated in dml soc. Reviewed-by:
Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following improvements: - Fix HDCP QUERY Error for eDP and Tiled - Insert smu busy status before sending another request Acked-by:
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Mustapha Ghaddar authored
[WHY] For dio_output_encoder ID we are relying on SW concept which is invisible to HW [HOW] Needed to create separate cases for when DPIA and non DPIA for dio link encoder ID Reviewed-by:
James Zhang <james.zhang@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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Oliver Logush authored
[why] Need to check if result register is busy before sending another request [how] Call method to check if result register is busy Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Oliver Logush <oliver.logush@amd.com> Tested-by:
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Felix Kuehling authored
MEC firmware sometimes sends signal interrupts without a valid context ID on end of pipe events that don't intend to signal any HSA signals. This triggers the slow path in kfd_signal_event_interrupt that scans the entire event page for signaled events. Detect these signals in the top half interrupt handler to stop processing them as early as possible. Because we now always treat event ID 0 as invalid, reserve that ID during process initialization. v2: Update firmware version checks to support more GPUs Signed-off-by:
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Haowen Bai authored
After alloc fail, we do not need to kfree. Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Signed-off-by:
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- 22 Apr, 2022 6 commits
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David Yu authored
Load ta fw during psp_init_sriov_microcode to enable XGMI. It is required to be loaded by both guest and host starting from Arcturus. Cap fw needs to be loaded first. Signed-off-by:
David Yu <David.Yu@amd.com> Reviewed-by:
Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by:
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Evan Quan authored
The adev->pm.mutx is already held at the beginning of amdgpu_dpm_compute_clocks/amdgpu_dpm_enable_uvd/amdgpu_dpm_enable_vce. But on their calling path, amdgpu_display_bandwidth_update will be called and thus its sub functions amdgpu_dpm_get_sclk/mclk. They will then try to acquire the same adev->pm.mutex and deadlock will occur. By placing amdgpu_display_bandwidth_update outside of adev->pm.mutex protection(considering logically they do not need such protection) and restructuring the call flow accordingly, we can eliminate the deadlock issue. This comes with no real logics change. Fixes: 3712e7a4 ("drm/amd/pm: unified lock protections in amdgpu_dpm.c") Reported-by:
Paul Menzel <pmenzel@molgen.mpg.de> Reported-by:
Arthur Marsh <arthur.marsh@internode.on.net> Link: https://lore.kernel.org/all/9e689fea-6c69-f4b0-8dee-32c4cf7d8f9c@molgen.mpg.de/ BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1957Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Tao Zhou authored
The fatal error handler is independent from general ras interrupt handler since there is no related IH ring. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
Add support for general RAS poison consumption handler. v2: remove callback function for poison consumption. Signed-off-by:
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Tao Zhou authored
Prepare for the implementation of poison consumption handler. v2: separate umc handler from poison creation. Signed-off-by:
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Yang Wang authored
simplify programming with existing functions. Signed-off-by:
Yang Wang <KevinYang.Wang@amd.com> Reviewed-by:
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- 21 Apr, 2022 6 commits
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Bokun Zhang authored
- In the latest version of the header, there is a variable name change. This should not cause any backward compatibility since the variable is at the same offset in the struct. Signed-off-by:
Bokun Zhang <Bokun.Zhang@amd.com> Acked-by:
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Bokun Zhang authored
- Clean up the identation in the header file Signed-off-by:
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Bokun Zhang authored
- Update MIT license header Signed-off-by:
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Alex Deucher authored
It's not used outside of dcn31_hubp.c. Reviewed-by:
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Miaoqian Lin authored
When dcn20_clk_src_construct() fails, we need to release clk_src. Fixes: 6f4e6361 ("drm/amd/display: Add Renoir resource (v2)") Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Signed-off-by:
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Haowen Bai authored
aux_rep only memset but no use at all, so we drop it. Signed-off-by:
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