1. 06 May, 2024 1 commit
    • Ho-Ren (Jack) Chuang's avatar
      memory tier: dax/kmem: introduce an abstract layer for finding, allocating,... · a72a30af
      Ho-Ren (Jack) Chuang authored
      memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types
      
      Patch series "Improved Memory Tier Creation for CPUless NUMA Nodes", v11.
      
      When a memory device, such as CXL1.1 type3 memory, is emulated as normal
      memory (E820_TYPE_RAM), the memory device is indistinguishable from normal
      DRAM in terms of memory tiering with the current implementation.  The
      current memory tiering assigns all detected normal memory nodes to the
      same DRAM tier.  This results in normal memory devices with different
      attributions being unable to be assigned to the correct memory tier,
      leading to the inability to migrate pages between different types of
      memory. 
      https://lore.kernel.org/linux-mm/PH0PR08MB7955E9F08CCB64F23963B5C3A860A@PH0PR08MB7955.namprd08.prod.outlook.com/T/
      
      This patchset automatically resolves the issues.  It delays the
      initialization of memory tiers for CPUless NUMA nodes until they obtain
      HMAT information and after all devices are initialized at boot time,
      eliminating the need for user intervention.  If no HMAT is specified, it
      falls back to using `default_dram_type`.
      
      Example usecase:
      We have CXL memory on the host, and we create VMs with a new system memory
      device backed by host CXL memory.  We inject CXL memory performance
      attributes through QEMU, and the guest now sees memory nodes with
      performance attributes in HMAT.  With this change, we enable the guest
      kernel to construct the correct memory tiering for the memory nodes.
      
      
      This patch (of 2):
      
      Since different memory devices require finding, allocating, and putting
      memory types, these common steps are abstracted in this patch, enhancing
      the scalability and conciseness of the code.
      
      Link: https://lkml.kernel.org/r/20240405000707.2670063-1-horenchuang@bytedance.com
      Link: https://lkml.kernel.org/r/20240405000707.2670063-2-horenchuang@bytedance.comSigned-off-by: default avatarHo-Ren (Jack) Chuang <horenchuang@bytedance.com>
      Reviewed-by: default avatar"Huang, Ying" <ying.huang@intel.com>
      Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawie.com>
      Cc: Alistair Popple <apopple@nvidia.com>
      Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: Dave Jiang <dave.jiang@intel.com>
      Cc: Gregory Price <gourry.memverge@gmail.com>
      Cc: Hao Xiang <hao.xiang@bytedance.com>
      Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
      Cc: Michal Hocko <mhocko@suse.com>
      Cc: Ravi Jonnalagadda <ravis.opensrc@micron.com>
      Cc: SeongJae Park <sj@kernel.org>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Vishal Verma <vishal.l.verma@intel.com>
      Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
      a72a30af
  2. 26 Apr, 2024 39 commits