- 22 Jun, 2017 2 commits
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Tom Rini authored
The binding bus/ti-gpmc.txt has been moved to memory-controllers/omap-gpmc.txt. Update all references to this in order to make reading and understanding a given binding easier. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc:Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Richard Weinberger <richard@nod.at> Cc: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Tom Rini <trini@konsulko.com> Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com>
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Tom Rini authored
The binding says that the compatible string must be "ti,am33xx-elm" but the code checks only for, and all functioning users set, this as "ti,am3352-elm" so correct the binding. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Richard Weinberger <richard@nod.at> Cc: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by:
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- 20 Jun, 2017 17 commits
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Prabhakar Kushwaha authored
All IFC version >= 1.0 use 28nm technology for SRAM. Here SRAM has a requirement to initialize before any read operation performed for avoiding ECC Error. So update condition check to initialize SRAM for all IFC version >= 1.0.0 Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by:
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Masahiro Yamada authored
Introduce some macros and helpers to avoid magic numbers and rename macros/functions for clarification. - We see '| 2' in several places. This means Data Cycle in MAP11 mode. The Denali User's Guide says bit[1:0] of MAP11 is like follows: b'00 = Command Cycle b'01 = Address Cycle b'10 = Data Cycle So, this commit added DENALI_MAP11_{CMD,ADDR,DATA} macros. - We see 'denali->flash_mem + 0x10' in several places, but 0x10 is a magic number. Actually, this accesses the data port of the Host Data/Command Interface. So, this commit added DENALI_HOST_DATA. On the other hand, 'denali->flash_mem' gets access to the address port, so DENALI_HOST_ADDR was also added. - We see 'index_addr(denali, cmd, 0x1)' in denali_erase(), but 0x1 is a magic number. 0x1 means the erase operation. Replace 0x1 with DENALI_ERASE. - Rename index_addr() to denali_host_write() for clarification - Denali User's Guide says MAP{00,01,10,11} for access mode. Match the macros with terminology in the IP document. - Rename struct members as follows: flash_bank -> active_bank (currently selected bank) flash_reg -> reg (base address of registers) flash_mem -> host (base address of host interface) devnum -> devs_per_cs (devices connected in parallel) bbtskipbytes -> oob_skip_bytes (number of bytes to skip in OOB) Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
Now this driver is ready to remove NAND_SKIP_BBTSCAN. The BBT descriptors in denali.c are equivalent to the ones in nand_bbt.c. There is no need to duplicate the equivalent structures. The with-oob decriptors do not work for this driver anyway. The bbt_pattern (offs = 8) and the version (veroffs = 12) area overlaps the ECC area. Set NAND_BBT_NO_OOB flag to use the no_oob variant of the BBT descriptors. Signed-off-by:
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Masahiro Yamada authored
As Russell and Lars stated in the discussion [1], using devm_k*alloc() with DMA is not a good idea. Let's use kmalloc (not kzalloc because no need for zero-out). Also, allocate the buffer as late as possible because it must be freed for any error that follows. [1] https://lkml.org/lkml/2017/3/8/693Signed-off-by:
Robin Murphy <robin.murphy@arm.com> Signed-off-by:
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Masahiro Yamada authored
For ecc->read_page() and ecc->write_page(), it is possible to call dma_map_single() against the given buffer. This bypasses the driver internal bounce buffer and save the memcpy(). Signed-off-by:
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Masahiro Yamada authored
Recent versions of this IP support automatic erased page detection. If an erased page is detected on reads, the controller does not set INTR__ECC_UNCOR_ERR, but INTR__ERASED_PAGE. The detection of erased pages is based on the number of zeros in a page; if the number of zeros is less than the value in the field ERASED_THRESHOLD, the page is assumed as erased. Please note ERASED_THRESHOLD specifies the number of zeros in a _page_ instead of an ECC chunk. Moreover, the controller does not provide a way to know the actual number of bitflips. Actually, an erased page (all 0xff) is not an ECC correctable pattern on the Denali ECC engine. In other words, there may be overlap between the following two: [1] a bit pattern reachable from a valid payload + ECC pattern within ecc.strength bitflips [2] a bit pattern reachable from an erased state (all 0xff) within ecc.strength bitflips So, this feature may intercept ECC correctable patterns, then replace [1] with [2]. After all, this feature can work safely only when ECC_THRESHOLD == 1, i.e. detect erased pages without any bitflips. This should be the case most of the time. If there is a bitflip or more, the driver will fallback to the software method by using nand_check_erased_ecc_chunk(). Strangely enough, the driver still has to fill the buffer with 0xff in case of INTR__ERASED_PAGE because the ECC correction engine has already manipulated the data in the buffer before it judges erased pages. Signed-off-by: -
Masahiro Yamada authored
The Denali IP adopts the syndrome page layout; payload and ECC are interleaved, with BBM area always placed at the beginning of OOB. The figure below shows the page organization for ecc->steps == 2: |----------------| |-----------| | | | | | | | | | Payload0 | | | | | | | | | | | | | | | |----------------| | in-band | | ECC0 | | area | |----------------| | | | | | | | | | | | Payload1 | | | | | | | | | | | |----------------| |-----------| | BBM | | | |----------------| | | |Payload1 (cont.)| | | |----------------| |out-of-band| | ECC1 | | area | |----------------| | | | OOB free | | | |----------------| |-----------| The current raw / oob accessors do not take that into consideration, so in-band and out-of-band data are transferred as stored in the device. In the case above, in-band: Payload0 + ECC0 + Payload1(partial) out-of-band: BBM + Payload1(cont.) + ECC1 + OOB-free This is wrong. As the comment block of struct nand_ecc_ctrl says, driver callbacks must hide the specific layout used by the hardware and always return contiguous in-band and out-of-band data. The current implementation is completely screwed-up, so read/write callbacks must be re-worked. Also, it is reasonable to support PIO transfer in case DMA may not work for some reasons. Actually, the Data DMA may not be equipped depending on the configuration of the RTL. This can be checked by reading the bit 4 of the FEATURES register. Even if the controller has the DMA support, dma_set_mask() and dma_map_single() could fail. In either case, the driver can fall back to the PIO transfer. Slower access would be better than giving up. Signed-off-by:
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Masahiro Yamada authored
It is not a good idea to re-use macros that represent a specific register bit field for the transfer direction. It is true that bit 8 indicates the direction for the MAP10 pipeline operation and the data DMA operation, but this is not valid across the IP. Use a simple flag (write: 1, read: 0) for the direction. Signed-off-by:
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Masahiro Yamada authored
Now struct nand_buf has only two members, so I see no reason for the separation. Signed-off-by:
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Masahiro Yamada authored
This driver stores the currently addressed page into denali->page, which is later read out by helper functions. While I am tackling on this driver, I often missed to insert "denali->page = page;" where needed. This makes page_read/write callbacks to get access to a wrong page, which is a bug hard to figure out. Instead, I'd rather pass the page via function argument because the compiler's prototype checks will help to detect bugs. For the same reason, propagate dma_addr to the DMA helpers instead of denali->buf.dma_buf . Signed-off-by:
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Masahiro Yamada authored
The current bank reset implementation polls the INTR_STATUS register until interested bits are set. This is not good because: - polling simply wastes time-slice of the thread - The while() loop may continue eternally if no bit is set, for example, due to the controller problem. The denali_wait_for_irq() uses wait_for_completion_timeout(), which is safer. We can use interrupt by moving the denali_reset_bank() call below the interrupt setup. Signed-off-by:
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Masahiro Yamada authored
The nand_scan_ident() iterates over maxchips, and calls nand_reset() for each. This driver currently passes the maximum number of banks (=chip selects) supported by the controller as maxchips. So, maxchips is typically 4 or 8. Usually, less number of NAND chips are connected to the controller. This can be a problem for ONFi devices. Now, this driver implements ->setup_data_interface() hook, so nand_setup_data_interface() issues Set Features (0xEF) command, which waits until the chip returns R/B# response. If no chip there, we know it never happens, but the driver still ends up with waiting for a long time. It will finally bail-out with timeout error and the driver will work with existing chips, but unnecessary wait will give a bad user experience. The denali_nand_reset() polls the INTR__RST_COMP and INTR__TIME_OUT bits, but they are always set even if not NAND chip is connected to that bank. To know the chip existence, INTR__INT_ACT bit must be checked; this flag is set only when R/B# is toggled. Since the Reset (0xFF) command toggles the R/B# pin, this can be used to know the actual number of chips, and update denali->max_banks. Signed-off-by:
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Masahiro Yamada authored
The NAND_CMD_SET_FEATURES support is missing from denali_cmdfunc(). We also see /* TODO: Read OOB data */ comment. It would be possible to add more commands along with the current implementation, but having ->cmd_ctrl() seems a better approach from the discussion with Boris [1]. Rely on the default ->cmdfunc() from the framework and implement the driver's own ->cmd_ctrl(). This transition also fixes NAND_CMD_STATUS and NAND_CMD_PARAM handling. NAND_CMD_STATUS was just faked by the register read, so the only valid bit was the WP bit. NAND_CMD_PARAM was completely broken; not only the command sent on the bus was NAND_CMD_STATUS instead of NAND_CMD_PARAM, but also the driver was only reading 8 bytes, while the parameter page contains several hundreds of bytes. Also add ->write_byte(), which is needed for write direction commands, ->read/write_buf(16), which will be used some commits later. ->read_word() is not used for now, but the core may call it in the future. Now, this driver can drop nand_onfi_get_set_features_notsupp(). [1] https://lkml.org/lkml/2017/3/15/97Signed-off-by:
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Masahiro Yamada authored
Simplify the interrupt handling and fix issues: - The register field view of INTR_EN / INTR_STATUS is different among IP versions. The global macro DENALI_IRQ_ALL is hard-coded for Intel platforms. The interrupt mask should be determined at run-time depending on the running platform. - wait_for_irq() loops do {} while() until interested flags are asserted. The logic can be simplified. - The spin_lock() guard seems too complex (and suspicious in a race condition if wait_for_completion_timeout() bails out by timeout). - denali->complete is reused again and again, but reinit_completion() is missing. Add it. Re-work the code to make it more robust and easier to handle. While we are here, also rename the jump label "failed_req_irq" to more appropriate "disable_irq". Signed-off-by: -
Masahiro Yamada authored
Handling timing parameters in a driver's own way should be avoided because it duplicates efforts of drivers/mtd/nand/nand_timings.c Besides, this driver hard-codes Intel specific parameters such as CLK_X=5, CLK_MULTI=4. Taking a certain device (Samsung K9WAG08U1A) into account by get_samsung_nand_para() is weird as well. Now, the core framework provides .setup_data_interface() hook, which handles timing parameters in a generic manner. While I am working on this, I found even more issues in the current code, so fixed the following as well: - In recent IP versions, WE_2_RE and TWHR2 share the same register. Likewise for ADDR_2_DATA and TCWAW, CS_SETUP_CNT and TWB. When updating one, the other must be masked. Otherwise, the other will be set to 0, then timing settings will be broken. - The recent IP release expanded the ADDR_2_DATA to 7-bit wide. This register is related to tADL. As commit 74a332e7 ("mtd: nand: timings: Fix tADL_min for ONFI 4.0 chips") addressed, the ONFi 4.0 increased the minimum of tADL to 400 nsec. This may not fit in the 6-bit ADDR_2_DATA in older versions. Check the IP revision and handle this correctly, otherwise the register value would wrap around. Signed-off-by:
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Masahiro Yamada authored
The function find_valid_banks() issues the Read ID (0x90) command, then compares the first byte (Manufacturer ID) of each bank with the one of bank0. This is equivalent to what nand_scan_ident() does. The number of chips is detected there, so this is unneeded. What is worse for find_valid_banks() is that, if multiple chips are connected to INTEL_CE4100 platform, it crashes the kernel by BUG(). This is what we should avoid. This function is just harmful and unneeded. Signed-off-by:
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Masahiro Yamada authored
The denali_cmdfunc() actually does nothing valuable for NAND_CMD_{PAGEPROG,READ0,SEQIN}. For NAND_CMD_{READ0,SEQIN}, it copies "page" to "denali->page", then denali_read_page(_raw) compares them just for the sanity check. (Inconsistently, this check is missing from denali_write_page(_raw).) The Denali controller is equipped with high level read/write interface, so let's skip unneeded call of cmdfunc(). If NAND_ECC_CUSTOM_PAGE_ACCESS is set, nand_write_page() will not call ->waitfunc hook. So, ->write_page(_raw) hooks should directly return -EIO on failure. The error handling of page writes will be much simpler. Signed-off-by:
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- 13 Jun, 2017 1 commit
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Alexandre Belloni authored
The Atmel NAND driver doesn't used anything from linux/platform_data/atmel.h, stop including it. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
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- 10 Jun, 2017 11 commits
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Masahiro Yamada authored
Add two compatible strings for UniPhier SoC family. "socionext,uniphier-denali-nand-v5a" is used on UniPhier sLD3, LD4, Pro4, sLD8. "socionext,uniphier-denali-nand-v5b" is used on UniPhier Pro5, PXs2, LD6b, LD11, LD20. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Masahiro Yamada authored
The Denali IP can automatically detect device parameters such as page size, oob size, device width, etc. and this driver currently relies on it. However, this hardware function is known to be problematic. [1] Due to a hardware bug, various misdetected cases were reported. That is why get_toshiba_nand_para() and get_hynix_nand_para() exist to fix-up the misdetected parameters. It is not realistic to add a new NAND device to the *black list* every time we are hit by a misdetected case. We would never be able to guarantee that all cases are covered. [2] Because this feature is unreliable, it is disabled on some platforms. The nand_scan_ident() detects device parameters in a more tested way. The hardware should not set the device parameter registers in a different, unreliable way. Instead, set the parameters from the nand_scan_ident() back to the registers. Signed-off-by: -
Masahiro Yamada authored
This driver was originally written for the Intel MRST platform with several platform-specific parameters hard-coded. Currently, the ECC settings are hard-coded as follows: #define ECC_SECTOR_SIZE 512 #define ECC_8BITS 14 #define ECC_15BITS 26 Therefore, the driver can only support two cases. - ecc.size = 512, ecc.strength = 8 --> ecc.bytes = 14 - ecc.size = 512, ecc.strength = 15 --> ecc.bytes = 26 However, these are actually customizable parameters, for example, UniPhier platform supports the following: - ecc.size = 1024, ecc.strength = 8 --> ecc.bytes = 14 - ecc.size = 1024, ecc.strength = 16 --> ecc.bytes = 28 - ecc.size = 1024, ecc.strength = 24 --> ecc.bytes = 42 So, we need to handle the ECC parameters in a more generic manner. Fortunately, the Denali User's Guide explains how to calculate the ecc.bytes. The formula is: ecc.bytes = 2 * CEIL(13 * ecc.strength / 16) (for ecc.size = 512) ecc.bytes = 2 * CEIL(14 * ecc.strength / 16) (for ecc.size = 1024) For DT platforms, it would be reasonable to allow DT to specify ECC strength by either "nand-ecc-strength" or "nand-ecc-maximize". If none of them is specified, the driver will try to meet the chip's ECC requirement. For PCI platforms, the max ECC strength is used to keep the original behavior. Newer versions of this IP need ecc.size and ecc.steps explicitly set up via the following registers: CFG_DATA_BLOCK_SIZE (0x6b0) CFG_LAST_DATA_BLOCK_SIZE (0x6c0) CFG_NUM_DATA_BLOCKS (0x6d0) For older IP versions, write accesses to these registers are just ignored. Signed-off-by:
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Masahiro Yamada authored
struct nand_ecc_caps was designed as flexible as possible to support multiple stepsizes (like sunxi_nand.c). So, we need to write multiple arrays even for the simplest case. I guess many controllers support a single stepsize, so here is a shorthand macro for the case. It allows to describe like ... NAND_ECC_CAPS_SINGLE(denali_pci_ecc_caps, denali_calc_ecc_bytes, 512, 8, 15); ... instead of static const int denali_pci_ecc_strengths[] = {8, 15}; static const struct nand_ecc_step_info denali_pci_ecc_stepinfo = { .stepsize = 512, .strengths = denali_pci_ecc_strengths, .nstrengths = ARRAY_SIZE(denali_pci_ecc_strengths), }; static const struct nand_ecc_caps denali_pci_ecc_caps = { .stepinfos = &denali_pci_ecc_stepinfo, .nstepinfos = 1, .calc_ecc_bytes = denali_calc_ecc_bytes, }; Signed-off-by: -
Masahiro Yamada authored
Driver are responsible for setting up ECC parameters correctly. Those include: - Check if ECC parameters specified (usually by DT) are valid - Meet the chip's ECC requirement - Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set The logic can be generalized by factoring out common code. This commit adds 3 helpers to the NAND framework: nand_check_ecc_caps - Check if preset step_size and strength are valid nand_match_ecc_req - Match the chip's requirement nand_maximize_ecc - Maximize the ECC strength To use the helpers above, a driver needs to provide: - Data array of supported ECC step size and strength - A hook that calculates ECC bytes from the combination of step_size and strength. By using those helpers, code duplication among drivers will be reduced. Signed-off-by: -
Masahiro Yamada authored
Use BIT() and GENMASK() for register field macros. This will make it easier to compare the macros with the register description in the Denali User's Guide. Signed-off-by:
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Masahiro Yamada authored
No need to use two struct resource pointers. Just reuse one. Signed-off-by:
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Matthias Lange authored
Signed-off-by:
Matthias Lange <matthias.lange@kernkonzept.com> Signed-off-by:
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Matthias Lange authored
This makes it easier to grep. Signed-off-by:
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Arvind Yadav authored
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Boris Brezillon authored
If we see unrecoverable ECC error, we need to count number of bitflips from all-ones and report correctable/uncorrectable according to that. Otherwise we report ECC failed on erased flash with single bit error. Signed-off-by:
Pavel Machek <pavel@denx.de> Reported-by:
Darwin Dingel <Darwin.Dingel@alliedtelesis.co.nz> Acked-by:
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- 01 Jun, 2017 9 commits
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Xiaolei Li authored
MT2712 NAND FLASH Controller is similar to MT2701 except those following: (1) MT2712 supports up to 148B spare size per 1KB size sector (the same with 74B spare size per 512B size sector). There are three new spare format: 61, 67, 74. (2) MT2712 supports up to 80 bit ecc strength. There are three new ecc strength level: 68, 72, 80. (3) MT2712 ECC encode parity data register's start offset is 0x300, and different with 0x10 of MT2701. (4) MT2712 improves ecc irq function. When ECC works in ECC_NFI_MODE, MT2701 will generate ecc irq number the same with ecc steps during page read. However, MT2712 can only generate one ecc irq. Changes of this patch are: (1) add two new variables named pg_irq_sel, encode_parity_reg0 in struct mtk_ecc_caps. (2) add new bitfield ECC_PG_IRQ_SEL for register ECC_IRQ_REG. (3) add ecc strength array of mt2712. (4) add spare size array of mt2712. (5) add mt2712 nfc and ecc device compatiable and data. Signed-off-by:Xiaolei Li <xiaolei.li@mediatek.com> Signed-off-by:
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Xiaolei Li authored
ECC strength and spare size supported may be different among MTK NAND FLASH Controller IPs. This patch contains changes as following: (1) add new struct mtk_nfc_caps to support different spare size. (2) add new struct mtk_ecc_caps to support different ecc strength. (3) remove ECC_CNFG_xBIT define, use a for loop to do ecc strength config. (4) remove PAGEFMT_SPARE_ define, use a for loop to do spare format config. (5) malloc ecc->eccdata buffer according to max ecc strength of this IP. Signed-off-by:
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Xiaolei Li authored
The register NFI_PAGEFMT is always 32 bits length, so it is better to do register program using writel() compare with writew(). Signed-off-by:
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Xiaolei Li authored
Add MT2712 NAND Flash Controller dt bindings documentation. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Arnd Bergmann authored
The newly added suspend/resume support causes a harmless warning: drivers/mtd/nand/atmel/nand-controller.c:2513:12: error: 'atmel_nand_controller_resume' defined but not used [-Werror=unused-function] This shuts up the warning with a __maybe_unused annotation. Fixes: b107007a7114 ("mtd: nand: atmel: Add PM ops") Signed-off-by:Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Masahiro Yamada authored
Drivers are supposed to set correct ecc->{size,strength,bytes} before calling nand_scan_tail(), but it does not complain about ecc->total bigger than oobsize. In this case, chip->scan_bbt() crashes due to memory corruption, but it is hard to debug. It would be kind to fail it earlier with a clear message. Signed-off-by: -
Boris Brezillon authored
READ0 is sometimes used to exit GET STATUS mode. When this is the case no address cycles are requested, and we can use this information to detect that READSTART should not be issued after READ0 or that we shouldn't wait for the chip to be ready. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Boris Brezillon authored
Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the full read/write page sequence, and waiting for a page to actually be programmed is part of this write-page sequence. This is also what is done in ->write_oob_xxx() hooks, so let's do that in ->write_page_xxx() as well to make it consistent. Signed-off-by: -
Boris Brezillon authored
SEQIN is supposed to be used when one wants to start programming a page. What we want here is just to change the column within the page, which is done with the RNDIN command. Fixes: 6956e238 ("mtd: nand: add tango NAND flash controller support") Cc: stable@vger.kernel.org Signed-off-by:
Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
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