- 29 Aug, 2019 4 commits
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Kevin Hilman authored
Tested-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
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git://github.com/BayLibre/clk-mesonKevin Hilman authored
Amlogic clk dt bindings changes for v5.4 - 3rd round * add sm1 peripheral controller bindings
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Kevin Hilman authored
Merge tag 'amlogic-drivers-2.1' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into v5.4/dt64-2 soc: amlogic: updates for v5.4 (round 2) - add power domain controller
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Neil Armstrong authored
Add the bindings for the Amlogic Everything-Else power domains, controlling the Everything-Else peripherals power domains. The bindings targets the Amlogic G12A and SM1 compatible SoCs, support for earlier SoCs will be added later. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 28 Aug, 2019 1 commit
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Neil Armstrong authored
Add support for the General Purpose Amlogic Everything-Else Power controller, with the first support for G12A and SM1 SoCs dedicated to the VPU, PCIe, USB, NNA, GE2D and Ethernet Power Domains. Signed-off-by:
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- 26 Aug, 2019 1 commit
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Neil Armstrong authored
Update the documentation to support clock driver for the Amlogic SM1 SoC and expose the GP1, DSU and the CPU 1, 2 & 3 clocks. SM1 clock tree is very close, the main differences are : - each CPU core can achieve a different frequency, albeit a common PLL - a similar tree as the clock tree has been added for the DynamIQ Shared Unit - has a new GP1 PLL used for the DynamIQ Shared Unit - SM1 has additional clocks like for CSI, NanoQ an other components Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com>
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- 20 Aug, 2019 8 commits
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Nishka Dasgupta authored
The variable np in function meson_gx_socinfo_init takes the return value of of_find_compatible_node, which gets a node but does not put it. If this node is not put it may cause a memory leak. Hence put np after its usefulness has been exhausted. Issue found with Coccinelle. Signed-off-by:
Nishka Dasgupta <nishkadg.linux@gmail.com> Reviewed-by:
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Neil Armstrong authored
Add support for the Amlogic SM1 Based SEI610 board. The SM1 SoC is a derivative of the G12A SoC Family with : - Cortex-A55 core instead of A53 - more power domains, including USB & PCIe - a neural network co-processor (NNA) - a CSI input and image processor - some changes in the audio complex, thus not yet enabled The SEI610 board is a derivative of the SEI510 board with : - removed ADC based touch button, replaced with 3x GPIO buttons - physical switch disabling on-board MICs - USB-C port for USB 2.0 OTG - On-board FTDI USB2SERIAL port for Linux console Audio, Display and USB support will be added later when support of the corresponding power domains will be added, for now they are kept disabled. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: fix minor typo regultor -> regulator] Signed-off-by:
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Neil Armstrong authored
Add the compatible for the Amlogic SM1 Based SEI610 board. Signed-off-by:
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Neil Armstrong authored
Add bindings for the new Amlogic SM1 SoC Family. It a derivative of the G12A SoC Family with : - Cortex-A55 core instead of A53 - more power domains - a neural network co-processor - a CSI input and image processor Signed-off-by:
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Neil Armstrong authored
Add the clk-measurer clocks IDs for the Amlogic SM1 SoC family. Signed-off-by:
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Neil Armstrong authored
Add the Amlogic SM1 Compatible for the clk-measurer IP. Reviewed-by:
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Neil Armstrong authored
Add the SoC IDs for the S905X3 Amlogic SM1 SoC. Reviewed-by:
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Jerome Brunet authored
Add the documentation and bindings for the resets provided by the g12a audio clock controller Reviewed-by:
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- 12 Aug, 2019 3 commits
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Neil Armstrong authored
Enable DVFS for the Odroid-N2 by setting the clock, OPP and supply for each cores of each CPU clusters. The first cluster uses the "VDDCPU_B" power supply, and the second cluster uses the "VDDCPU_A" power supply. Each power supply can achieve 0.73V to 1.01V using 2 distinct PWM outputs clocked at 800KHz with an inverse duty-cycle. DVFS has been tested by running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25fReviewed-by:
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Christian Hewitt authored
The Khadas VIM3 uses the Amlogic S922X or A311S SoC, both based on the Amlogic G12B SoC family, on a board with the same form factor as the VIM/VIM2 models. It ships in two variants; basic and pro which differ in RAM and eMMC size: - 2GB (basic) or 4GB (pro) LPDDR4 RAM - 16GB (basic) or 32GB (pro) eMMC 5.1 storage - 16MB SPI flash - 10/100/1000 Base-T Ethernet - AP6398S Wireless (802.11 a/b/g/n/ac, BT5.0) - HDMI 2.1 video - 1x USB 2.0 + 1x USB 3.0 ports - 1x USB-C (power) with USB 2.0 OTG - 3x LED's (1x red, 1x blue, 1x white) - 3x buttons (power, function, reset) - IR receiver - M2 socket with PCIe, USB, ADC & I2C - 40pin GPIO Header - 1x micro SD card slot A common meson-g12b-khadas-vim3.dtsi is added to support both S922X and A311D SoCs supported by two variants of the board. Signed-off-by:
Christian Hewitt <christianshewitt@gmail.com> Signed-off-by:
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git://github.com/BayLibre/clk-mesonKevin Hilman authored
Amlogic clock changes for v5.4 * Migrate to new clock description method * Add DVFS support to g12 # gpg: Signature made Mon 12 Aug 2019 02:11:32 AM PDT # gpg: using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85 # gpg: Good signature from "Jerome Brunet <jbrunet@baylibre.com>" [full] # gpg: aka "Jerome Brunet <jerome@liltaz.com>" [full] # gpg: aka "Jerome Brunet <jerome.brunet@gmail.com>" [full] * tag 'clk-meson-v5.4-1' of git://github.com/BayLibre/clk-meson: clk: meson: g12a: expose CPUB clock ID for G12B clk: meson: g12a: add notifiers to handle cpu clock change clk: meson: add g12a cpu dynamic divider driver clk: core: introduce clk_hw_set_parent() clk: meson: remove clk input helper clk: meson: remove ee input bypass clocks clk: meson: clk-regmap: migrate to new parent description method clk: meson: meson8b: migrate to the new parent description method clk: meson: axg: migrate to the new parent description method clk: meson: gxbb: migrate to the new parent description method clk: meson: g12a: migrate to the new parent description method clk: meson: remove ao input bypass clocks clk: meson: axg-aoclk: migrate to the new parent description method clk: meson: gxbb-aoclk: migrate to the new parent description method clk: meson: g12a-aoclk: migrate to the new parent description method clk: meson: axg-audio: migrate to the new parent description method clk: meson: g12a: fix hifi typo in mali parent_names
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- 09 Aug, 2019 20 commits
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Christian Hewitt authored
Move amediatech,x96-max and seirobotics,sei510 to the S905D2 section and update the S905D2 description to S905D2/X2/Y2. Signed-off-by:
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Kevin Hilman authored
The Arm per-CPU architected timers stop ticking in suspend, when the SCP powers down the CPUs. Flag that in the DT. Signed-off-by: -
Christian Hewitt authored
Meson g12b ships with a low-speed (S922X) and high-speed (A311D) variant so remove cpu_opp_table nodes in meson-g12b.dtsi and create two new dtsi that can be included in device-specific dts files. Opp points were taken from the vendor BSP kernel. Also make meson-g12b-odroid-n2.dts include the new meson-g12b-s922x.dtsi. Signed-off-by:
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Christian Hewitt authored
The Khadas VIM3 uses the Amlogic S922X or A311S SoC, both based on the Amlogic G12B SoC family, on a board with the same form factor as the VIM/VIM2 models. It ships in two variants; basic and pro which differ in RAM and eMMC size: - 2GB (basic) or 4GB (pro) LPDDR4 RAM - 16GB (basic) or 32GB (pro) eMMC 5.1 storage - 16MB SPI flash - 10/100/1000 Base-T Ethernet - AP6398S Wireless (802.11 a/b/g/n/ac, BT5.0) - HDMI 2.1 video - 1x USB 2.0 + 1x USB 3.0 ports - 1x USB-C (power) with USB 2.0 OTG - 3x LED's (1x red, 1x blue, 1x white) - 3x buttons (power, function, reset) - IR receiver - M2 socket with PCIe, USB, ADC & I2C - 40pin GPIO Header - 1x micro SD card slot Signed-off-by:
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Neil Armstrong authored
Add a specific compatible for the Amlogic G12B bases A311D SoC used in the Khadas VIM3. Signed-off-by:
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Neil Armstrong authored
Add a specific compatible for the Amlogic G12B family based S922X SoC to differentiate with the A311D SoC from the same family. Signed-off-by:
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Maxime Jourdan authored
This enables the video decoder for GXBB, GXL and GXM chips Signed-off-by:
Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by:
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Maxime Jourdan authored
Add the base video decoder node compatible with the meson vdec driver, for GX* chips. Signed-off-by:
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Maxime Jourdan authored
The first version of the bindings is missing a generic compatible that is used by the base node (GX), and then extended by the SoC device trees (GXBB, GXL, GXM) Also change the example to use "video-codec" instead of "video-decoder", as the former is the one used in almost all cases when it comes to video decode/encode accelerators. Signed-off-by:
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Jerome Brunet authored
If unspecified in DT, the fifo sizes are not automatically detected by the dwmac1000 dma driver and the reported fifo sizes default to 0. Because of this, flow control will be turned off on the device. Add the fifo sizes provided by the datasheets in the SoC in DT so flow control may be enabled if necessary. Signed-off-by:
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Neil Armstrong authored
Add the OPP table taken from the HardKernel Odroid-N2 DTS. The Amlogic G12B SoC seems to available in 2 types : - low-speed: Cortex-A73 Cluster up to 1,704GHz - high-speed: Cortex-A73 Cluster up to 2.208GHz The Cortex-A73 Cluster can be clocked up to 1,896GHz for both types. The Vendor Amlogic A311D OPP table are slighly different, with lower voltages than the HardKernel S922X tables but seems to be high-speed type. This adds the conservative OPP table with the S922X higher voltages and the maximum low-speed OPP frequency. The values were tested to be stable on an HardKernel Odroid-N2 board running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations for both clusters and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25fSigned-off-by:
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Neil Armstrong authored
Enable DVFS for the U200, SEI520 and X96-Max Amlogic G12A based board by setting the clock, OPP and supply for each CPU cores. The CPU cluster power supply can achieve 0.73V to 1.01V using a PWM output clocked at 800KHz with an inverse duty-cycle. DVFS has been tested by running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25fReviewed-by:
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Neil Armstrong authored
Add the OPP table taken from the vendor u200 and u211 DTS. The Amlogic G12A SoC seems to available in 3 types : - low-speed: up to 1,8GHz - mid-speed: up to 1,908GHz - high-speed: up to 2.1GHz And the S905X2 opp voltages are slightly higher than the S905D2 OPP voltages for the low-speed table. This adds the conservative OPP table with the S905X2 higher voltages and the maximum low-speed OPP frequency. The values were tested to be stable on an Amlogic U200 Reference Board, SeiRobotics SEI510 and X96 Max Set-Top-Boxes running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25fSigned-off-by:
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Neil Armstrong authored
Add the ao_pinctrl subnode for the pwm_a function on GPIOE_2. Reviewed-by:
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Neil Armstrong authored
To simplify the representation of differences betweem the G12A and G12B SoCs, move the common nodes into a meson-g12-common.dtsi file and express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi. This separation will help for DVFS and future Amlogic SM1 Family support. The sd_emmc_a quirk is added in the g12a/g12b since since it's already known the sd_emmc_a controller is fixed in the next SM1 SoC family. Signed-off-by:
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Jerome Brunet authored
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Neil Armstrong authored
Expose the CPUB clock id to add DVFS to the second CPU cluster of the Amlogic G12B SoC. Reviewed-by:
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Neil Armstrong authored
In order to implement clock switching for the CLKID_CPU_CLK and CLKID_CPUB_CLK, notifiers are added on specific points of the clock tree : cpu_clk / cpub_clk | \- cpu_clk_dyn | | \- cpu_clk_premux0 | | |- cpu_clk_postmux0 | | | |- cpu_clk_dyn0_div | | | \- xtal/fclk_div2/fclk_div3 | | \- xtal/fclk_div2/fclk_div3 | \- cpu_clk_premux1 | |- cpu_clk_postmux1 | | |- cpu_clk_dyn1_div | | \- xtal/fclk_div2/fclk_div3 | \- xtal/fclk_div2/fclk_div3 \ sys_pll / sys1_pll This for each cluster, a single one for G12A, two for G12B. Each cpu_clk_premux1 tree is marked as read-only and CLK_SET_RATE_NO_REPARENT, to be used as "parking" clock in a safe clock frequency. A notifier is added on each cpu_clk_premux0 to detech when CCF want to change the frequency of the cpu_clk_dyn tree. In this notifier, the cpu_clk_premux1 tree is configured to use the xtal clock and then the cpu_clk_dyn is switch to cpu_clk_premux1 while CCF updates the cpu_clk_premux0 tree. A notifier is added on each sys_pll/sys1_pll to detect when CCF wants to change the PLL clock source of the cpu_clk. In this notifier, the cpu_clk is switched to cpu_clk_dyn while CCF updates the sys_pll/sys1_pll frequency. A third small notifier is added on each cpu_clk / cpub_clk and cpu_clk_dyn, add a small delay at PRE_RATE_CHANGE/POST_RATE_CHANGE to let the other notofiers change propagate before changing the cpu_clk_premux0 and sys_pll clock trees. This notifier set permits switching the cpu_clk / cpub_clk without any glitches and using a safe parking clock while switching between sub-GHz clocks using the cpu_clk_dyn tree. This setup has been tested and validated on the Amlogic G12A and G12B SoCs running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25fSigned-off-by:
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Neil Armstrong authored
Add a clock driver for the cpu dynamic divider, this divider needs to have a flag set before setting the divider value then removed while writing the new value to the register. This drivers implements this behavior and will be used essentially on the Amlogic G12A and G12B SoCs for cpu clock trees. Signed-off-by:
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Neil Armstrong authored
Introduce the clk_hw_set_parent() provider call to change parent of a clock by using the clk_hw pointers. This eases the clock reparenting from clock rate notifiers and implementing DVFS with simpler code avoiding the boilerplates functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent(). Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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- 05 Aug, 2019 3 commits
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Christian Hewitt authored
Add the SoC ID for the A311D Amlogic SoC. Signed-off-by:
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Xavier Ruppen authored
When powering off the Odroid N2, the tflash_vdd regulator is automatically turned off by the kernel. This is a problem when issuing the "reboot" command while using an SD card. The boot ROM does not power this regulator back on, blocking the reboot process at the boot ROM stage, preventing the SD card from being detected. Adding the "regulator-always-on" property fixes the problem. Signed-off-by:
Xavier Ruppen <xruppen@gmail.com> Suggested-by:
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Neil Armstrong authored
Enable the IR receiver controller on the SEI510 board. Signed-off-by:
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