- 04 Oct, 2021 28 commits
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: rebase v3: switch some if statements to switch statements v4: add yellow carp fix (Yifan) v5: squash in fixes for YC and GS (Alex) Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Rather than hardcoding based on asic_type, use the IP discovery table to configure the driver. Only tested on Navi10 so far. Reviewed-by:
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Alex Deucher authored
Drive the asic setup from the IP discovery table rather than hardcoded settings based on asic type. Reviewed-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: squash in gmc fixes v3: rebase Acked-by:
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Alex Deucher authored
Bind to all 0x1002 GPU devices. For now we explicitly return -ENODEV for generic bindings. Remove this check once IP discovery based checking is in place. v2: rebase (Alex) Reviewed-by:
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Alex Deucher authored
Once we claim all 0x1002 PCI display class devices, we will need to filter out devices owned by radeon. v2: rename radeon id array to make it more clear that the devices are not supported by amdgpu. add r128, mach64 pci ids as well Acked-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: rebase, squash in navi10 fixes (Alex) Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by:
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Alex Deucher authored
Use IP versions rather than asic_type to differentiate IP version specific features. v2: rebase Acked-by:
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Alex Deucher authored
Add initial support for all navi based parts. v2: rebase Acked-by:
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Alex Deucher authored
So they can be driven by IP dicovery table. Reviewed-by:
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Alex Deucher authored
So we can track grab the appropriate XGMI info out of the IP discovery table. Reviewed-by:
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Alex Deucher authored
Prerequisite for using IP versions in the driver rather than asic type. v2: Use IP_VERSION() macro instead of new function Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: -
Alex Deucher authored
So we can check the IP versions directly rather than using asic type. Reviewed-by:
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Alex Deucher authored
Useful for debugging and new asic validation. Reviewed-by:
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Alex Deucher authored
Consolidate harvesting information. Reviewed-by:
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John Clements authored
clear error count when persistant harvesting is not enabled Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Harry Wentland authored
[Why] For some reason we're defining DP 2.0 definitions inside our driver. Now that patches to introduce relevant definitions are slated to be merged into drm-next this is causing conflicts. In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:33: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:70: In file included from ./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mode.h:36: ./include/drm/drm_dp_helper.h:1322:9: error: 'DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER' macro redefined [-Werror,-Wmacro-redefined] ^ ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:881:9: note: previous definition is here ^ 1 error generated. [How] Guard all display driver defines with #ifndef for now. Once we pull in the new definitions into amd-staging-drm-next we will follow up and drop definitions from our driver and provide follow-up header updates for any addition DP 2.0 definitions required by our driver. We also ensure drm_dp_helper.h is included before dc_dp_types.h. v3: Ensure drm_dp_helper.h is included before dc_dp_types.h v2: Add one missing endif Reviewed-by:Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Tao Zhou authored
In ras poison mode, page retirement will be handled by the irq handler of the module which consumes corrupted data. v2: rename ras_process_cb to ras_poison_consumption_handler. move the handler's implementation from ASIC specific file to common file. v3: call gpu reset for xGMI connected mode. Signed-off-by:Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Prike Liang authored
In the s2idle stress test sdma resume fail occasionally,in the failed case GPU is in the gfxoff state.This issue may introduce by firmware miss handle doorbell S/R and now temporary fix the issue by forcing exit gfxoff for sdma resume. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Zhan Liu authored
[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
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- 29 Sep, 2021 12 commits
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Zhan Liu authored
This patch is to add cyan_skillfish asic header files. Signed-off-by:
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Andrey Grodzovsky authored
To support libdrm tests. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Handle all DMA IOMMU group related dependencies before the group is removed and we try to access it after free. v2: Move the actul handling function to TTM Signed-off-by:
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Ernst Sjöstrand authored
We use the number_instance index that we get from the fw discovery blob to index into an array for example. Update error messages (Alex) Signed-off-by:
Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by:
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Arnd Bergmann authored
The two AMD drivers have their own custom offsetof() implementation that now triggers a warning with recent versions of clang: drivers/gpu/drm/radeon/radeon_atombios.c:133:14: error: performing pointer subtraction with a null pointer has undefined behavior [-Werror,-Wnull-pointer-subtraction] Change all the instances to use the normal offsetof() provided by the kernel that does not have this problem. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Yang Li authored
Use resource_size function on resource object instead of explicit computation. Clean up coccicheck warning: ./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:905:10-13: ERROR: Missing resource_size with res Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Reviewed-by:
Amos Kong <kongjianjun@gmail.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Arnd Bergmann authored
The overflow check in amdgpu_bo_list_create() causes a warning with clang-14 on 64-bit architectures, since the limit can never be exceeded. drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c:74:18: error: result of comparison of constant 256204778801521549 with expression of type 'unsigned int' is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (num_entries > (SIZE_MAX - sizeof(struct amdgpu_bo_list)) ~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The check remains useful for 32-bit architectures, so just avoid the warning by using size_t as the type for the count. Fixes: 920990cb ("drm/amdgpu: allocate the bo_list array after the list") Reviewed-by: -
Simon Ser authored
On GFX9+, format modifiers are always enabled and ensure the frame-buffers can be scanned out at ADDFB2 time. On GFX8-, format modifiers are not supported and no other check is performed. This means ADDFB2 IOCTLs will succeed even if the tiling isn't supported for scan-out, and will result in garbage displayed on screen [1]. Fix this by adding a check for tiling flags for GFX8 and older. The check is taken from radeonsi in Mesa (see how is_displayable is populated in gfx6_compute_surface). Changes in v2: use drm_WARN_ONCE instead of drm_WARN (Michel) [1]: https://github.com/swaywm/wlroots/issues/3185Signed-off-by:
Simon Ser <contact@emersion.fr> Acked-by:
Michel Dänzer <mdaenzer@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Tom St Denis authored
The commit 2766534b added the offset header but didn't add the masks. This adds the masks based on what was selected for the offsets. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Acked-by:
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Charlene Liu authored
[why] pci deviceid not passed to dal dc, without proper break, dcn2.x falls into dcn3.x code path [how] pass in pci deviceid, and break once dal_version initialized. Reviewed-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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George Shen authored
[Why] Recently debugging efforts have involved setting/checking the X.Y value used during payload allocation. Current output for Y was calculated with incorrect bitshift. Y value is also not human readable. [How] Refactor logging into separate function. Fix Y calculation error and format output to be human readable. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why/How] Theoretically rare corner case where ceil(Y) results in rounding up to an integer. If this happens, the 1 should be carried over to the X value. Reviewed-by:
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