Merge tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes

From Paul Walmsley:

OMAP clock, powerdomain, clockdomain, and hwmod fixes intended for the
early v3.4-rc series.  Also contains an HSMMC integration refinement
of an earlier hardware bug workaround.

* tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending:
  ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions
  ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status
  ARM: OMAP2+: hwmod: Restore sysc after a reset
  ARM: OMAP2+: omap_hwmod: Allow io_ring wakeup configuration for all modules
  ARM: OMAP3: clock data: fill in some missing clockdomains
  ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock
  ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL
  ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch()
  ARM: OMAP AM3517/3505: clock data: change EMAC clocks aliases
  ARM: OMAP: clock: fix race in disable all clocks
  ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocks
  ARM: OMAP3xxx: clock data: fix DPLL4 CLKSEL masks
  ARM: OMAP3xxx: HSMMC: avoid erratum workaround when transceiver is attached
  ARM: OMAP44xx: clockdomain data: correct the emu_sys_clkdm CLKTRCTRL data

With commit c334bc15 (ARM: make mach/io.h include optional), PCMCIA was
broken. PCMCIA depends on __io() returning a valid i/o address, and most
ARM platforms require IO_SPACE_LIMIT be set to 0xffffffff for PCMCIA. This
needs a better fix with a fixed i/o address mapping, but for now we just
restore things to the previous behavior.

This fixes at91, omap1, pxa and sa11xx. pxa needs io.h if PCI is enabled,
but PCMCIA is not. sa11xx already has IO_SPACE_LIMIT set to 0xffffffff,
so it doesn't need an io.h.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Joachim Eastwood <joachim.eastwood@jotron.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Andrew Victor <linux@maxim.org.za>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Tested-by: Paul Parsons <lost.distance@yahoo.com> (pxa270)
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge branch 'v3.4-samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes

* 'v3.4-samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Fix compiler warning in dma.c file
  ARM: EXYNOS: fix ISO C90 warning
  ARM: EXYNOS: use chip_id reg in uncompress to select uart base phys
  ARM: EXYNOS: fix CONFIG_DEBUG_LL
  ARM: S3C24XX: fix missing common.h in mach-s3c24xx/

Merge branch 'v3.4-cpufreq-exynos-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes

* 'v3.4-cpufreq-exynos-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  EXYNOS: fix dependency for EXYNOS_CPUFREQ

From Tony Lindgren:

Note that this also contains a set of fixes that are not regressions
or oopses to properly deal with the smsc911x regulator issue.

Basically the regulators must be per board file as the regulators
can also come from drivers, such as twl4030. So it's best to dumb
down gpmc-smsc911x.c to not even care about the regulators.

* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP: fix section mismatches in usb-host.c
  ARM: OMAP2+: Fix omap2+ build error
  ARM: OMAP2+: smsc911x: Add fixed board regulators
  ARM: OMAP2+: smsc911x: Remove regulator support from gmpc-smsc911x
  ARM: OMAP2+: smsc911x: Remove unused rate calculation
  ARM: OMAP2+ smsc911x: Fix possible stale smsc911x flags
  ARM: OMAP2+: smsc911x: Remove odd gpmc_cfg/board_data redirection
  ARM: OMAP3+: fix oops triggered in omap_prcm_register_chain_handler(v1)
  ARM: OMAP2+: OPP: allow OPP enumeration to continue if device is not present
  arm: omap3: pm34xx.c: Replace printk() with appropriate pr_*()
  arm: omap3: pm34xx.c: Fix omap3_pm_init() error out paths
  ARM: OMAP4: Workaround the OCP synchronisation issue with 32K synctimer.
  ARM: OMAP4: prm: fix interrupt register offsets
  ARM: OMAP: hwmod: Use sysc_fields->srst_shift and get rid of hardcoded SYSC_TYPE2_SOFTRESET_MASK

* 'at91-fixes' of git://github.com/at91linux/linux-at91:
  ARM: at91: dt: remove unit-address part for memory nodes
  ARM: at91: fix check of valid GPIO for SPI and USB
  USB: ehci-atmel: add needed of.h header file
  ARM: at91/NAND DT bindings: add comments
  ARM: at91/at91sam9x5.dtsi: fix NAND ale/cle in DT file
  USB: ohci-at91: trivial return code name change
  USB: ohci-at91: change maximum number of ports
  USB: ohci-at91: rework and fix initialization
  ARM: at91/dts: USB host vbus is active low
  ARM: at91/USB host: specify and handle properly vbus_pin_active_low
  USB: ohci-at91: fix vbus_pin_active_low handling
  ARM: at91/at91sam9x5: add clkdev entries for DMA controllers

Merge branch 'for-3.4/fixes-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into fixes

* 'for-3.4/fixes-for-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  gpio: tegra: Iterate over the correct number of banks
  gpio: tegra: fix register address calculations for Tegra30

Fixes the following warning:
warning: 'dma_dmamask' defined but not used [-Wunused-variable]
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

ISO C90 forbids mixed declarations and code.
Fix it.
Signed-off-by: Il Han <corone.il.han@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Merge branches 'clock_fixes_3.4rc', 'clockdomain_fixes_3.4rc', 'hsmmc_erratum_2_1_1_128_refine_3.4rc1', 'hwmod_data_fixes_a_3.4rc', 'hwmod_fixes_a2_3.4rc' and 'powerdomain_fixes_a_3.4rc' into omap-fixes-a2-for-3.4rc-branch

In the SYSC_TYPE1_XXX_MASK configuration, SYSC_XXX_SHIFT macro
is used which is not defined anywhere in the kernel.
Until now the build was going through successfully, since it
is not being used anywhere in kernel.

This bug got introduced by the commit
358f0e63 ("OMAP3: hwmod: support
to specify the offset position of various SYSCONFIG register bits.")
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

omap_hwmod_softreset() does not seem to wait for reset status
after doing a softreset. Make it use _ocp_softreset() instead
which does this correctly.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Anand Gadiyar <gadiyar@ti.com>
Cc: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

After a softreset, make sure the sysc settings are correctly
restored.
Reported-by: Anand Gadiyar <gadiyar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shubhrajyoti D <shubhrajyoti@ti.com>
[paul@pwsan.com: combined post-reset SYSCONFIG reload code into the
 _reset() function to avoid duplication and future mistakes]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Some modules doesn't have SYSC_HAS_ENAWAKEUP bit available (ex: usb
host uhh module) in absence of this flag
omap_hwmod_enable/disable_wakeup avoids configuring pad mux wakeup
capability.

Configure sysc if SYSC_HAS_ENAWAKEUP is available and for other cases
try enabling/disabling wakeup from mux_pad pins.

Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
[paul@pwsan.com: updated function kerneldoc documentation]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Several clocks are missing clockdomains.  This can cause problems with
the hwmod and power management code.  Fill these in.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Matt Porter <mporter@ti.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>

All DPLLs except USB are in ALWON powerdomain. Make sure the
clkdm/pwrdm for USB DPLL (l3init) is turned on before attempting
a DPLL relock. So, mark the database accordingly.

Without this fix, it was seen that DPLL relock fails while testing
relock in a loop of USB DPLL.

Cc: Nishanth Menon <nm@ti.com>
Tested-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

According to OMAP4 TRM Table 3-1183, CM_CLKSEL_DPLL_USB register defines
following fields for multiplication and division factors:

DPLL_MULT (bits 19:8) DPLL multiplier factor (2 to 4095)
DPLL_DIV (bits 7:0) DPLL divider factor (0 to 255)
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Ameya Palande <ameya.palande@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Commit b1cbdb00 ("OMAP: clockdomain: Wait for powerdomain to be ON
when using clockdomain force wakeup") was assuming that
pwrdm_state_switch() does wait for the powerdomain transition which is
not the case.  The missing wait for the powerdomain transition
violates the sequence which the hardware expects, which causes power
management failures on some devices.

Fix this API by adding the pwrdm_wait_transition().
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: added some more details in the commit log]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

When Tegra30 support was added to the Tegra GPIO driver, a few places
which iterated over all banks were not converted to use the variable
tegra_gpio_bank_count rather than hard-coding the bank count. Fix this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>

Tegra20 and Tegra30 share the same register layout within registers, but
the addresses of the registers is a little different. Fix the driver to
cope with this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>

This fixes the CPUFREQ dependency for regarding EXYNOS SoCs
such as EXYNOS4210, EXYNOS4X12 and EXYNOS5250. Its cpufreq
driver should be built with selection of SoC arch part.
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Dave Jones <davej@redhat.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Because of the inclusion of skeleton.dtsi, the memory node is
named "memory" we where not modifying the already included one
but creating a new one. It caused bad memory node detection during
early_init_dt_scan_memory() so we modify them.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: devicetree-discuss@lists.ozlabs.org

SPI chip select pins have to be checked by gpio_is_valid().
The USB host overcurrent_pin checking was missing.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Compilation error in case of non-DT configuration without this
of.h header file.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>

Add comments to NAND "gpios" property to make it clearer.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>

Change number of ports to 3 for newer SoCs. Modify pdata structure
and ohci-at91 code that was dealing with ports information and check
of port indexes.
Several coding style errors have been addresses as the patch was touching
affected lines of code and was producing errors while run through
checkpatch.pl.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>

The DT information are filled in a pdata structure and then passed on
to the usual check code of the probe function. Thus we do not need to
redo the gpio checking and irq configuration in the DT-related code.
On the other hand, we setup GPIO direction in driver for vbus and
overcurrent. It will be useful when moving to pinctrl subsystem.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>

Change vbus gpio configuration in .dts files to switch to
active low configuration.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: stable <stable@vger.kernel.org>

Due to an error while handling vbus_pin_active_low in ohci-at91 driver,
the specification of this property was not good in devices/board files.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: stable <stable@vger.kernel.org>         [3.2+]

The information is not properly taken into account
for {get|set}_power() functions.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Cc: stable <stable@vger.kernel.org>		[3.2+]

Signed-off-by: Dima Zavin <dima@android.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

addruart cannot read from the physical address of the chipid
register, that will fail as soon as the mmu is turned on.
Fixing it to read from the physical or virtual address depending
on the mmu state also does not work, because there is a period
between head.S and exynos_map_io where the mmu is on, the uart
is mapped and used, but the chipid mapping is not yet present.

Fix addruart to use the ARM Main ID cp15 register to determine
if the core is Cortex A15 (EXYNOS5) or not (EXYNOS4).
Signed-off-by: Colin Cross <ccross@android.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Rename EMAC clocks to match driver expectations: both davinci_emac and
davinci_mdio drivers call clk_get(dev, NULL) so we have to provide
("davinci_emac", NULL) and ("davinci_mdio.0", NULL) clocks instead of
("davinci_emac", "emac_clk") and ("davinci_emac", "phy_clk") resp.

Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Tested-by: Yegor Yefremov <yegorslists@googlemail.com>
Tested-by: Matt Porter <mporter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

clk_disable_unused is invoked when CONFIG_OMAP_RESET_CLOCKS=y.
Since clk_disable_unused is called as lateinitcall, there can
be more than a few workqueues executing off secondary CPU(s).
The current code does the following:
a) checks if clk is unused
b) holds lock
c) disables clk
d) unlocks

Between (a) and (b) being executed on CPU0, It is possible to
have a driver executing on CPU1 which could do a get_sync->clk_get
(and increase the use_count) of the clock which was just about
to be disabled by clk_disable_unused.

We ensure instead that the entire list traversal is protected by
the lock allowing for parent child clock traversal which could be
potentially be done by runtime operations to be safe as well.
Reported-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

CLKS signal for McBSP ports can be selected from internal (PRCM) or
external (ABE_CLKS pin) source.  To be able to use existing code we
need to create clock aliases consistent among OMAP2/3/4.

Based on a patch from Péter Ujfalusi <peter.ujfalusi@ti.com>;
the patch description above is his.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Péter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

Commit 2a9f5a4d "OMAP3 clock: remove unnecessary duplicate of dpll4_m2_ck,
added for 36xx" consolidated dpll4 clock structures between 34xx and 36xx,
but left 34xx CLKSEL masks for most dpll4 related clocks, which causes
clock code to not behave correctly when booting on DM3730 with higher
(36xx only) divisors set:
[    0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:375 omap2_init_clksel_parent+0x104/0x114()
[    0.000000] clock: dpll4_m3_ck: init parent: could not find regval 0
[    0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:194 omap2_clksel_recalc+0xd4/0xe4()
[    0.000000] clock: Could not find fieldval 0 for clock dpll4_m3_ck parent dpll4_ck

Fix this by switching to 36xx masks, as valid divisors will be limited
by clksel_rate lists.

Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

If transceiver is attached to a MMC host of ES2.1 OMAP35xx, it seems
2.1.1.128 erratum doesn't apply and there is no data corruption,
probably because of different signal timing. The workaround for this
erratum disables multiblock reads, which causes dramatic loss of
performance (over 75% slower), so avoid it when transceiver is present.

Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
[paul@pwsan.com: edited commit message slightly]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

According to the 4430 ES2.0 TRM vX Table 3-744 "CM_EMU_CLKSTCTRL",
the emu_sys clockdomain data in mainline is incorrect.

The emu_sys clockdomain does not support the DISABLE_AUTO state, and
instead it supports the FORCE_WAKEUP state.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>