- 07 Apr, 2021 1 commit
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 (take two) - Add bias support for the R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, - Miscellaneous cleanups and improvements.
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- 31 Mar, 2021 2 commits
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Linus Walleij authored
Add depends on OF so we don't get weird build errors on randconfig. Also order selects the same as the other drivers for pure aestetic reasons. Reported-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Álvaro Fernández Rojas authored
The current implementation of bcm6362_set_gpio() produces the following warning on x86_64: drivers/pinctrl/bcm/pinctrl-bcm6362.c: In function 'bcm6362_set_gpio': drivers/pinctrl/bcm/pinctrl-bcm6362.c:503:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 503 | (uint32_t) desc->drv_data, 0); | ^ Modify the code to make it similar to bcm63268_set_gpio() in order to fix the warning. Fixes: 705791e2 ("pinctrl: add a pincontrol driver for BCM6362") Signed-off-by:Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210330103225.3949-1-noltari@gmail.comReviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
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- 29 Mar, 2021 25 commits
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Linus Walleij authored
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.13-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.13-1 * Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly
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Wan Jiabing authored
linux/io.h has been included at line 6, so remove the duplicate include at line 18. Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Reviewed-by:
Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210323013727.135571-1-wanjiabing@vivo.comSigned-off-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs to different functions. BCM6318 is similar to BCM6328 with the addition of a pad register, and the GPIO meaning of the mux register changes based on the GPIO number. Co-developed-by:
Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6318 SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210324081923.20379-22-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6318 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs to different functions. Depending on the mux, these are either single pin configurations or whole pin groups. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM63268 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in the BCM63268 family SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 GPIOs onto alternative functions. Not all are documented. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6368 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6368 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual GPIO pins to the LED controller, to be available by the integrated wifi, or other functions. It also supports overlay groups, of which only NAND is documented. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6362 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6362 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different functions onto the GPIO pins. It does not support configuring individual pins but only whole groups. These groups may overlap, and still require the directions to be set correctly in the GPIO register. In addition the functions register controls other, not directly mux related functions. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6358 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6358 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as GPIOs, as LEDs for the integrated LED controller, or various other functions. Its pincontrol mux registers also control other aspects, like switching the second USB port between host and device mode. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6328 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6328 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a helper for registering BCM63XX pin controllers. Co-developed-by:
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Álvaro Fernández Rojas authored
Convert existing BCM6345 GPIO binding documentation to YAML and add binding documentation for the GPIO controller found in BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
This is needed for properly registering GPIO regmap as a child of a regmap pin controller. Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Link: https://lore.kernel.org/r/20210324081923.20379-3-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
The current code doesn't check if GPIOLIB_IRQCHIP is enabled, which results in a compilation error when trying to build gpio-regmap if CONFIG_GPIOLIB_IRQCHIP isn't enabled. Fixes: 6a45b0e2 ("gpiolib: Introduce gpiochip_irqchip_add_domain()") Suggested-by:
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- 25 Mar, 2021 7 commits
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Andy Shevchenko authored
In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, which is disabled here, it is not a problem because IRQ framework serializes descriptor handling. Remove disabling IRQ part in the handler. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com>
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Geert Uytterhoeven authored
The Rockchip GPIO and pin control modules are only present on Rockchip SoCs. Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the user about this driver when configuring a kernel without Rockchip platform support. Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and automatically selected when needed. By making it tristate and user-selectable, it became visible for everyone. Fixes: be786ac5 ("pinctrl: rockchip: make driver be tristate module") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210316134059.2377081-1-geert+renesas@glider.beSigned-off-by:
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Zhiyong Tao authored
When multiple threads operate on the same register resource which include multiple pin, It will make the register resource wrong to control. So we add lock to avoid the case. Signed-off-by:
Zhiyong Tao <zhiyong.tao@mediatek.com> Link: https://lore.kernel.org/r/20210321033150.15380-2-zhiyong.tao@mediatek.comSigned-off-by:
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 - Add pin groups for the green and high8 subsets of the Video IN (VIN) pins on R-Car H3 ES2.0+, R-Car M3-W/M3-W+, R-Car M3-N, and R-Car E3.
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Hanna Hawa authored
A System Error (SError, followed by kernel panic) was detected when trying to print the supported pins in a pinctrl device which supports multiple pins per register. This change fixes the pcs_pin_dbg_show() in pinctrl-single driver when bits_per_mux is not zero. In addition move offset calculation and pin offset in register to common function. Fixes: 4e7e8017 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Signed-off-by:
Hanna Hawa <hhhawa@amazon.com> Reviewed-by:
Tony Lindgren <tony@atomide.com> Reviewed-by:
Drew Fustini <drew@beagleboard.org> Link: https://lore.kernel.org/r/20210319152133.28705-4-hhhawa@amazon.comSigned-off-by:
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Hanna Hawa authored
Remove unused parameter 'pin_pos' from pcs_add_pin(). Signed-off-by:
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Hanna Hawa authored
Remove unused parameter 'num_pins_in_register' from pcs_allocate_pin_table(). Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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- 24 Mar, 2021 5 commits
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Geert Uytterhoeven authored
Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, using the common R-Car bias handling. Note that on RZ/G1 SoCs, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132619.3938128-7-geert+renesas@glider.be
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Geert Uytterhoeven authored
Currently, the common R-Car bias handling supports pin controllers with either: 1. Separate pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers, for controlling both pin pull-up and pin pull-down, 2. A single pin Pull-Up control register (PUPR), for controlling pin pull-up. Add support for a variant of #2, where some bits in the single pin Pull-Up control register (PUPR) control pin pull-down instead of pin pull-up. This is the case for the "ASEBRK#/ACK" pin on R-Car M2-W, M2-N, and E2, and the "ACK" pin on RZ/G1M, RZ/G1N, RZ/G1E, and RZ/G1C. To describe such a register, SoC-specific drivers need to provide two instances of pinmux_bias_reg: a first one with the puen field filled in, listing pins with pull-up functionality, and a second one with the pud field filled in, listing pins with pull-down functionality. Signed-off-by: -
Geert Uytterhoeven authored
Add PORT_GP_CFG_7() and PORT_GP_7() helper macros, to be used by the r8a7791 subdriver. Signed-off-by:
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Geert Uytterhoeven authored
The pin control sub-drivers for SH/R-Mobile SoCs contain almost identical bias handling. The only SoC-specific part is the mapping from pin numbers to PORTnCR registers. Reduce code duplication by factoring out the bias handling to the common pinctrl.c code. Use a callback to handle the pin/register mapping. Signed-off-by:
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Geert Uytterhoeven authored
The Renesas Pin Function Controller driver uses two header files: - sh_pfc.h, for use by both core code and SoC-specific drivers, - core.h, for internal use by the core code only. Hence move the R-Car bias helper declarations from core.h to sh_pfc.h, and drop the inclusion of core.h from SoC-specific drivers that no longer need it. Signed-off-by:
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