- 13 Mar, 2012 40 commits
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Dave Airlie authored
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-core-next * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (57 commits) drm/nouveau: map first page of mmio early and determine chipset earlier drm/nvd0/disp: disconnect encoders before reprogramming them drm/nvd0/disp: move syncs/magic setup to or mode_set drm/nouveau/dp: account for channel coding overhead in link training drm/nvd0/disp: fix dcb sor link matching in supervisor handler drm/nvd0/disp: initial implementation of displayport drm/nouveau/dp: make dp dpms function common, call from sor code instead drm/nv50/hwsq: some nv92 fixes drm/nouveau/dp: move all nv50/sor-specific code out of nouveau_dp.c drm/nouveau/dp: make functions for executing various bios tables drm/nouveau/pm: fix oops if chipset has no pm support at all drm/nouveau/bios: rework vbios shadowing drm/nouveau/bios: attempt acpi rom fetch before pcirom drm/nvd0/disp: attempt to handle more than 2 crtcs if possible drm/nvc0/vram: get part count from PUNITS drm/nv40/pm: fix fanspeed regression drm/nouveau/pm: several fixes for nvc0 memory timings drm/nvc0/pm: restrict pll mode to clocks that can actually use it drm/nouveau/dp: fix bad comparison in dp_link_train_commit() drm/nouveau/mxm: call mxmi to determine revision before calling mxms ...
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
NVIDIA appear to do these around the same place they do the MODE_CTRL methods, and for DP at least we need to bash some extra bits in "syncs" to keep EVO happy. It's a bit of a guess as to the 6/8bpc, but i have no better idea yet. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
GF119 will use this too. Signed-off-by: -
Martin Peres authored
The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92 This fixes some reclocking issues on my newly acquired nv92 Signed-off-by:
Martin Peres <martin.peres@labri.fr> Signed-off-by:
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Ben Skeggs authored
Off-chip encoders (which we don't support yet anyway), and newer chipsets (such as NVD9...), will need their own code for this. Signed-off-by: -
Ben Skeggs authored
More code to do the same thing, but will make it easier to handle various changes that could possibly happen the the VBIOS tables. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
Refactored to allow shadowing of VBIOS images longer than 64KiB, which allows us to pass the VBIOS checksum test on certain boards. There's also a workaround for reading the PROM VBIOS on some chipsets. Signed-off-by: -
Ben Skeggs authored
There's cards out there with completely messed up PCIROM images that have a perfectly valid signature.. Sigh! Signed-off-by: -
Ben Skeggs authored
Theoretically handles CRTC2/CRTC3, should any GF119 out there actually have them enabled. The room is there for the regs etc, so why not :) Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Roy Spliet authored
This patch fixes two small issues in timing generation as spotted on several NVCx cards. In addition, the header of the file is updated to also contain (some of) the current developers of this code. Signed-off-by:
Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by:
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Ben Skeggs authored
Fixes reclocking failure on some chips where we attempted to set PDAEMON to PLL mode. Signed-off-by: -
Xi Wang authored
The comparison (lpre == DP_TRAIN_PRE_EMPHASIS_9_5) is always false: lpre is initialized as (lane & 0x0c) >> 2, which is at most 3, while DP_TRAIN_PRE_EMPHASIS_9_5 is defined as (3 << 3). Signed-off-by:
Xi Wang <xi.wang@gmail.com> Signed-off-by:
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Ben Skeggs authored
There's a HP laptop out there where the MXM version in the VBIOS doesn't match what the ACPI implementation is expecting. These tables will accept 0x00 to MXMS to return latest version, but *only* if MXMI has been called first.. Signed-off-by: -
Ben Skeggs authored
This patch fixes an oops cause by pm_trigger accessing the (uninitialised) crtc list. Reported-by:
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Ben Skeggs authored
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Christoph Bumiller authored
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Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by:
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Ben Skeggs authored
v2 (Emil Velikov <emil.l.velikov@gmail.com>): - Fixed a regression on certain nv50 IGP due to not passing the correct target type to nv50_vm_addr() Signed-off-by:
Emil Velikov <emil.l.velikov@gmail.com> Tested-by:
Johannes Obermayr <johannesobermayr@gmx.de>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Fixes minor flickering on NVS295 when at perflvl 0. Signed-off-by:
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Ben Skeggs authored
Goes a long way to correcting NVS295 memory reclocking issues. Signed-off-by:
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Ben Skeggs authored
There's some "extended" GDDR3 chipsets out there with EMRS2 settings that change the layout of MRS/EMRS1 bitmaps.. Sigh.. Still need to track down how exactly we're supposed to handle this. Signed-off-by:
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Martin Peres authored
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Ben Skeggs authored
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
This will probably result in more lines of code, however, we're going to have at least 3 slightly different implementations of this very soon and I'd rather keep the ram reclocking logic separate from the hw specifics. DDR2/DDR3/GDDR3 implemented thus far, others will be added as necessary. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
Statically generating the PFB register and MR values for each timing set turns out to be insufficient. There's at least one (so far) known piece of information which effects MR values which is stored in the perflvl entry on some chipsets (and in another table on later ones), which is disconnected from the timing table entries. After this change we will generate a timing set based on an input clock frequency instead, and have this data stored in the performance level data. Signed-off-by:
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