- 13 Aug, 2018 11 commits
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Mikita Lipski authored
[why] We are disabling clock source while other pipes are still using it, because we don't verify the number of pipes that share it. [how] - Adding a function in resources to return the number of pipes sharing the clock source. - Checking that no one is sharing the clock source before disabling Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Mikita Lipski authored
[why] HDMI and DVI share the same PHY clock and single link DVI and HDMI both use 4 lanes, so they should be allowed to be sharing the same clock source if all other parameters are satisfied. [how] Change a check for general DVI to Dual DVI. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
[Why] DOUBLE_BUFFER_EN bit is getting cleared before enable blanking. That leads to CRTC_BLANK_DATA_EN is getting updated immediately. [How] Get DOUBLE_BUFFER_EN bit set, the same as DCE110. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Emily Deng authored
Entity init should after ring init, as the entity's sched_rq's initialization is in ring init. SWDEV-161495 Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Emily Deng authored
Entity init should after ring init, as the entity's sched_rq's initialization is in ring init. SWDEV-161495 Signed-off-by:
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Likun Gao authored
Setup psp firmware loading for VCN, and make VCN block booting from tmr mac address. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Likun Gao authored
Add VCN support in PSP driver Signed-off-by:
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Likun Gao authored
Add the new firmware id for VCN into the enum Signed-off-by:
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James Zhu authored
Update tmr mc address with firmware loading address which is returned from PSP firmware Signed-off-by:
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James Zhu authored
amdgpu IP blocks booting need Trust Memory Region(tmr) mc address of its firmware which is loaded by PSP Signed-off-by:
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- 10 Aug, 2018 3 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
More fixes for 4.19: - Fixes for scheduler - Fix for SR-IOV - Fixes for display Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180809200052.2777-1-alexander.deucher@amd.com
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git://git.pengutronix.de/git/pza/linuxDave Airlie authored
drm/imx: ipu-v3 plane offset and IPU id fixes - Fix U/V plane offsets for odd vertical offsets. Due to wrong operator order, the y offset was not rounded down properly for vertically chroma subsampled planar formats. - Fix IPU id number for boards that don't have an OF alias for their single IPU in the device tree. This is necessary to support imx-media on i.MX51 and i.MX53 SoCs. Signed-off-by:
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git://git.pengutronix.de/git/pza/linuxDave Airlie authored
drm/imx: use suspend/resume helpers, add ipu-v3 V4L2 XRGB32/XBGR32 support - Convert imx_drm_suspend/resume to use the drm_mode_config_helper_suspend/ resume functions. - Add support for V4L2_PIX_FMT_XRGB32/XBGR32, corresponding to DRM_FORMAT_XRGB8888/BGRX8888, respectively. Signed-off-by:
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- 09 Aug, 2018 2 commits
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Emily Deng authored
Extend the timeout for recovering vram bos from shadows on sr-iov to cover the worst case scenario for timeslices and VFs Under runtime, the wait fence time could be quite long when other VFs are in exclusive mode. For example, for 4 VF, every VF's exclusive timeout time is set to 3s, then the worst case is 9s. If the VF number is more than 4,then the worst case time will be longer. The 8s is the test data, with setting to 8s, it will pass the TDR test for 1000 times. SWDEV-161490 Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
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Nayan Deshmukh authored
We no longer have sched parameter so remove its description as well Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Signed-off-by:
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- 07 Aug, 2018 13 commits
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2018-08-06' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Fix gvt compilation broken on a silent conflict on fixes vs next merge - Fix runtime PM for LPE audio - Revert on ICL workaround - Interactive RPS mode - Fix for PSR sink status report Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2018-08-02' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Fixes an oops on the DP CEC code and a memory leak on the vkms driver. Signed-off-by:
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
Fixes for 4.19: - Fix UVD 7.2 instance handling - Fix UVD 7.2 harvesting - GPU scheduler fix for when a process is killed - TTM cleanups - amdgpu CS bo_list fixes - Powerplay fixes for polaris12 and CZ/ST - DC fixes for link training certain HMDs - DC fix for vega10 blank screen in certain cases From: Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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https://git.pengutronix.de/git/lst/linuxDave Airlie authored
From: Lucas Stach <l.stach@pengutronix.de> "not much to de-stage this time. Changes from Philipp and Souptick to use memset32 more and switch the fault handler to the new vm_fault_t and two small fixes for issues that can be hit in rare corner cases from me." Signed-off-by:
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git://git.armlinux.org.uk/~rmk/linux-armDave Airlie authored
From: Russell King <rmk@armlinux.org.uk> As per the patches posted, discussed and tested by Peter Rosin, this converts TDA998x to a bridge driver, while still allowing Armada and TI LCDC to continue using it as they always have done. It also gets rid of the private .fill_modes function, and tweaks the TMDS divider calculation to be more correct to the available information. [airlied: fixed two conflicts] Signed-off-by:
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git://linux-arm.org/linux-ldDave Airlie authored
From: Liviu Dudau <Liviu.Dudau@arm.com> "I managed to loose track of a few patches for HDLCD while focusing on Mali DP and found them again when investigating an issue with the way HDLCD behaves on teardown. They can go into drm-next for one of the v4.19-rcX if you're not going to do another pull request before the merge window." Signed-off-by:
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Russell King authored
The serializer PLL divider is a power-of-two divider, so our calculation which assumes that it's a numerical divider is incorrect. Replace it with one that results in a power-of-two divider value instead. Tested with all supported modes with a Samsung S24C750. Tested-by:
Peter Rosin <peda@axentia.se> Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk>
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Russell King authored
We can achieve the same effect via the get_modes() method, rather than wrapping the fill_modes helper. Tested-by:
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Russell King authored
Move the mode_valid() implementation to the bridge instead of the connector, as we're checking the bridge's capabilities. Tested-by:
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Russell King authored
Register the bridge outside of the component helper as we have drivers that wish to use the tda998x without its encoder. Tested-by:
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Russell King authored
Cleanup the code a little from the effects of the previous changes: - Move tda998x_destroy() to be above tda998x_create() - Use 'dev' directly in tda998x_create() where appropriate. Tested-by:
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Russell King authored
Move the tda998x_priv allocation inside tda998x_create() and simplify the tda998x_create()'s arguments. Pass the same to tda998x_destroy(). Tested-by:
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Russell King authored
Convert tda998x to a bridge driver with built-in encoder support for compatibility with existing component drivers. Tested-by:
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- 06 Aug, 2018 11 commits
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Lucas Stach authored
drm_sched_job_finish() is a work item scheduled for each finished job on a unbound system workqueue. This means the workers can execute out of order with regard to the real hardware job completions. If this happens queueing a timeout worker for the first job on the ring mirror list is wrong, as this may be a job which has already finished executing. Fix this by reorganizing the code to always queue the worker for the next job on the list, if this job hasn't finished yet. This is robust against a potential reordering of the finish workers. Also move out the timeout worker cancelling, so that we don't need to take the job list lock twice. As a small optimization list_del is used to remove the job from the ring mirror list, as there is no need to reinit the list head in the job we are about to free. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
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Hersen Wu authored
[why] for vega, dp set_panel_mode is handled by psp firmware. dal should not program the register again. [how] dal does not program panel mode. Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Mikita Lipski authored
[why] When programming tonga's connector's backend we didn't take in account that HDMI's colour depth might be more than 8bpc therefore we need to add a switch statement that would adjust the pixel clock accordingly. [how] Add a switch statement updating clock by its appropriate coefficient. Signed-off-by:
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Dmytro Laktyushkin authored
[Why] We seem to have an issue where high enough display clock will not get set properly during S3 resume if we only call vbios once [How] Expand condition of display clock programming to happen even when cached display clock matches requested display clock Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The pointer for integrated_info can be NULL which causes the system to do a null pointer deference and hang on boot. [How] Add a check to ensure that integrated_info is not null before enabling DP ss. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Mikita Lipski authored
[why] Prevent clock source sharing between HDMI and DP connectors. DP shouldn't be sharing its ref clock with phy clock, which caused an issue of older ASICS booting up with multiple diplays plugged in. [how] Add an extra check that would prevent HDMI and DP sharing clk. Signed-off-by:
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Hersen Wu authored
[why] dp hbr2 eye diagram pattern for raven asic is not stabled. workaround is to use tp4 pattern. But this should not be applied to asic before raven. [how] add new bool varilable in asic caps. for raven asic, use the workaround. for carrizo, vega, do not use workaround. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The calculated values for actual disp_clk_khz were ignored when notifying pplib of the new display requirements. In order to honor DFS bypass clocks from the hardware, the calculated value should be used. [How] The return value for set_dispclk is now assigned back into new_clocks and correctly carried through into dccg->clks.phyclk_khz. When notifying pplib of new display requirements dccg->clks.phyclk_khz is used instead of dce.dispclk_khz. The value of dce.dispclk_khz was never explicitly set to anything before. A 15% higher display clock value than calculated is no longer requested for dce110 since it now makes use of the calculated value. Since dce112 makes use of dce110's set_bandwidth but not its update_clocks it needs to have the value correctly carried through. Signed-off-by:
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David Francis authored
[Why] Custom degamma lut functions are a feature we would like to support on compatible hardware [How] In atomic check, convert from array of drm_color_lut to dc_transfer_func. On hardware commit, allow for possibility of custom degamma. Both are based on the equivalent regamma pipeline. Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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David Francis authored
[Why] In the dce112 function to destroy the resource pool, engines (the aux engines) is destroyed twice. This has no ill effects but is a tad redundant. [How] Remove the redundant call Signed-off-by:
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