- 22 Nov, 2021 40 commits
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Jiapeng Chong authored
Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.c:1554 pp_asic_reset_mode_2() warn: inconsistent indenting. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Amber Lin authored
Instead of hard coding the number of sdma engines and the number of sdma_xgmi engines in the device_info table, get the number of toal SDMA instances from amdgpu. The first two engines are sdma engines and the rest are sdma-xgmi engines unless the ASIC doesn't support XGMI. v2: add kfd_ prefix to non static function names Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Felix Kuehling authored
Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset to the fixed address of the VF register for hdp_v*_flush_hdp. Signed-off-by:
Bokun Zhang <bokun.zhang@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Stanley.Yang authored
if smu support ECCTABLE, driver can message smu to get ecc_table then query umc error info from ECCTABLE v2: optimize source code makes logical more reasonable Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Stanley.Yang authored
support ECC TABLE message, this table include umc ras error count and error address v2: add smu version check to query whether support ecctable call smu_cmn_update_table to get ecctable directly Signed-off-by:Evan Quan <evan.quan@amd.com> Reviewed-by:
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Stanley.Yang authored
add message smu to query error information v2: rename message_smu to ecc_info Signed-off-by: -
Stanley.Yang authored
update smu driver if version to 0x08 to avoid mismatch log A version mismatch can still happen with an older FW Signed-off-by:
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Alex Deucher authored
Disable vblanks immediately to save power. I think this was missed when we merged DC support. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1781Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Yang Li authored
Clang static analysis reports this error drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2870:7: warning: Dereference of null pointer [clang-analyzer-core.NullDereference] if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { ^ top_pipe_to_program being NULL is caught as an error But then it is used to report the error. So add a check before using it. Reported-by:Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Bernard Zhao authored
In function dc_sink_destruct, kfree will check pointer, no need to check again. This change is to cleanup the code a bit. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Bernard Zhao authored
This change is to cleanup the code a bit. Acked-by:
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Bernard Zhao authored
In function amdgpu_get_xgmi_hive, when kobject_init_and_add failed There is a potential memleak if not call kobject_put. Reviewed-by:
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Bernard Zhao authored
This change is to cleanup the code style a bit. Signed-off-by:
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Bernard Zhao authored
This change is to remove useless break after return. Signed-off-by:
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Ye Guojin authored
This was found by coccicheck: ./drivers/gpu/drm/amd/display/dc/core/dc_resource.c, 2516, 7-9, WARNING possible condition with no effect (if == else) hdmi_info.bits.YQ0_YQ1 is always YYC_QUANTIZATION_LIMITED_RANGE. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Ye Guojin <ye.guojin@zte.com.cn> Signed-off-by:
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Jiapeng Chong authored
Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:622 dmub_srv_cmd_execute() warn: inconsistent indenting. Reported-by:
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hongao authored
amdgpu_connector_vga_get_modes missed function amdgpu_get_native_mode which assign amdgpu_encoder->native_mode with *preferred_mode result in amdgpu_encoder->native_mode.clock always be 0. That will cause amdgpu_connector_set_property returned early on: if ((rmx_type != DRM_MODE_SCALE_NONE) && (amdgpu_encoder->native_mode.clock == 0)) when we try to set scaling mode Full/Full aspect/Center. Add the missing function to amdgpu_connector_vga_get_mode can fix this. It also works on dvi connectors because amdgpu_connector_dvi_helper_funcs.get_mode use the same method. Signed-off-by:
hongao <hongao@uniontech.com> Signed-off-by:
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Roman Li authored
[Why] After commit ("drm/amdgpu/display: add support for multiple backlights") number of eDPs is defined while registering backlight device. However the panel's extended caps get updated once before register call. That leads to regression with extended caps like oled brightness control. [How] Update connector ext caps after register_backlight_device Fixes: 7fd13bae ("drm/amdgpu/display: add support for multiple backlights") Link: https://www.reddit.com/r/AMDLaptops/comments/qst0fm/after_updating_to_linux_515_my_brightness/Signed-off-by:Roman Li <Roman.Li@amd.com> Tested-by:
Samuel Čavoj <samuel@cavoj.net> Acked-by:
Jasdeep Dhillon <Jasdeep.Dhillon@amd.com> Signed-off-by:
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Candice Li authored
Fix race condition failure during UMC UE injection. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Tao Zhou authored
If gpu reset is triggered by ras fatal error, tell it to smu in mode-1 reset message. v2: move mode-1 reset function to aldebaran_ppt.c since it's aldebaran specific currently. Signed-off-by:
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shaoyunl authored
In SRIOV configuration, the reset may failed to bring asic back to normal but stop cpsch already been called, the start_cpsch will not be called since there is no resume in this case. When reset been triggered again, driver should avoid to do uninitialization again. Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Lijo Lazar authored
Print Navi1x fine grained clocks in a consistent manner with other SOCs. Don't show aritificial DPM level when the current clock equals min or max. Signed-off-by:
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Evan Quan authored
Just bail out if the target IP block is already in the desired powergate/ungate state. This can avoid some duplicate settings which sometimes may cause unexpected issues. Link: https://lore.kernel.org/all/YV81vidWQLWvATMM@zn.tnic/ Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214921 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=215025 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1789Signed-off-by:
Borislav Petkov <bp@suse.de> Reviewed-by:
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Sung Joon Kim authored
[why] Change causing issue. Need to revert the change. Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Fix issue that secondary display goes blank on Non DCN31. - Adjust flushing data in DMCUB - Revert patches which cause regression in hadnling MPO/Link encoder assignment - Correct the setting within MSA of DP2.0 - Adjustment for DML isolation - Fix FIFO erro in fast boot sequence - Enable DSC over eDP - Adjust the DSC power off sequence Reviewed-by:
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Yi-Ling Chen authored
[WHY] After unloading driver, driver would not disable DSC function. At next loading driver, driver would power all DSC engines off. When driver powered the active DSC off, the screen would be gray until reprograming DSC relatived register correcntly. [HOW] 1. Remove DSC Power down code into init_pipes() 2. Depend on the OTG mapping information and DSC status to skip power off for the working DSC. Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Tested-by:
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Anthony Koo authored
- Fix ARR39-C issue with scaled integer addition in rb func Reviewed-by:
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Anthony Koo authored
Acked-by:
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hvanzyll authored
[What] This change allows adjustment to the Visual Confirm height border. [Why] Aids debugging and testing [How] Use the existing infrastructure to implement logic to draw borders Reviewed-by:
Harry VanZyllDeJong <hvanzyll@amd.com> Tested-by:
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Brandon Syu authored
[WHY] With eDP DSC enabled and set 4K 60Hz, there would be screen corruption when booting to OS or enabling the driver. [HOW] Avoid powering down VDD when we cannot apply eDP fast boot. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Brandon Syu <Brandon.Syu@amd.com> Tested-by:
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Mikita Lipski authored
[why] - Adding a DM interface to enable DSC over eDP on Linux - DSC over eDP will allow to power savings by reducing the bandwidth required to support panel's modes - Apply link optimization algorithm to reduce link bandwidth when DSC is enabled [how] - Read eDP panel's DSC capabilities - Apply DSC policy on eDP panel based on its DSC capabilities - Enable DSC encoder's on the pipe - Enable DSC on panel's side by setting DSC_ENABLE DPCD register - Adding link optimization algorithm to reduce link rate or lane count based Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
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Angus Wang authored
[WHY] Previous LTTPR change has caused a regression that led to an issue where LTTPR is disabled [HOW] Extended changes from previous fix to DCN30X Reviewed-by:
Wesley Chalmers <wesley.chalmers@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Angus Wang <angus.wang@amd.com> Signed-off-by:
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Xu, Jinze authored
[Why] In fast boot sequence, when change dispclk, otg is disabled but digfe is enabled. This may cause dig fifo error. [How] Reset dig fifo after enable otg. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
JinZe.Xu <JinZe.Xu@amd.com> Tested-by:
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Jun Lei authored
[why] DML itself is SW only, putting the logic as part of resource makes it hw dependent and thus impossible to compile separately from dc. Separate compilation is critical for unit testing as well as bbox tool development [how] create new dml wrapper. Copy logic from the validation functions into dml wrapper as base implementation. Dml wrapper has internal/static implementations for all helpers, and does not reference other functions. It may reference dc structures/types for convenience. This change now has all the changes for DML isolation squashed into one. Reviewed-by:
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Wenjing Liu authored
[why] There is a bug in MSA programming sequence that mistakenly set MSA vsp/hsp to 1 for positive polarity. This is incorrect. Reviewed-by:
Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Angus Wang authored
[WHY] The previous changes for fixing MPO underflow with multiple display connected caused a regression where the machine runs into a hang when doing multiple driver pnp with multiple displays connected [HOW] Reverted offending change Reviewed-by:
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Nicholas Kazlauskas authored
[Why] We're currently flushing commands that had been previously been flushed or are currently being processed by the DMCUB when we don't immediately wait for idle after command execution. [How] Avoiding reflushing the data by keeping track of the last wptr. We'll treat this as the actual rptr by creating a copy of the inbox and modifying the copy's rptr. Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Ahmad Othman authored
[Why] Due to integration issues with branch merging, a regression happened that prevented secondary displays from lighting up or enabling certain features [How] Separated the new logic to be for DCN31 only and retained pre DCN31 logic for all other ASICs Reviewed-by:
Ahmad Othman <Ahmad.Othman@amd.com> Tested-by:
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Ramesh Errabolu authored
MMIO/DOORBELL BOs encode control data and should be pinned in GTT domain before enabling PCIe connected peer devices in accessing it Signed-off-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Reviewed-by:
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Ramesh Errabolu authored
Accounting system to track amount of available memory (system, TTM and VRAM of a device) relies on BO's domain. The change is to rely instead on allocation flag indicating BO type - VRAM, GTT, USERPTR, MMIO or DOORBELL Signed-off-by:
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