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The serial peripheral interface (SPI) module implemented on Freescale Vybrid
platform provides a synchronous serial bus for communication between Vybrid
and the external peripheral device.
The SPI supports full-duplex, three-wire synchronous transfer, has TX/RX FIFO
with depth of four entries.

This driver is the SPI master mode driver and has been tested on Vybrid
VF610TWR board.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Chao Fu  <b44548@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>

It now needs the architecture dependant DMA driver.
Signed-off-by: Mark Brown <broonie@linaro.org>

Enable the build of drivers which don't have any real build time
dependency on their architecture or platform with COMPILE_TEST,
providing better build time coverage.
Signed-off-by: Mark Brown <broonie@linaro.org>

Keystone2 SOCs share the SPI IP block with DaVinci based SOCs. Update
the config bits so that its usable on Keystone2 based SOCs.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

The filter function used by the rspi driver is part of the DMAE controller
driver so if the DMA controller driver is somehow disabled then the rspi
driver will fail to build.
Signed-off-by: Mark Brown <broonie@linaro.org>

New spi controller(version 3) is integrated into Blackfin
60x processor. Comparing to bf5xx spi controller, we support
32 bits word size and independent receive and transmit DMA
channels now. Also mode 0 and 2 (CPHA = 0) can get fully
supported becasue cs line may be controlled by the software.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

I got a build error today that made me realize that it is not
possible to build a kernel for a SiRF platform without enabling
CONFIG_PRIMA2, since a lot of common code depends on CONFIG_PRIMA2.

This fixes all occurences that appear like common SiRF code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Mike Turquette <mturquette@linaro.org>

CAVIUM_OCTEON_SOC most place we used to use CPU_CAVIUM_OCTEON.  This
allows us to CPU_CAVIUM_OCTEON in places where we have no OCTEON SOC.

Remove CAVIUM_OCTEON_SIMULATOR as it doesn't really do anything, we can
get the same configuration with CAVIUM_OCTEON_SOC.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-ide@vger.kernel.org
Cc: linux-edac@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: spi-devel-general@lists.sourceforge.net
Cc: devel@driverdev.osuosl.org
Cc: linux-usb@vger.kernel.org
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Patchwork: https://patchwork.linux-mips.org/patch/5295/

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

GENERIC_GPIO is now equivalent to GPIOLIB and features that depended on
GENERIC_GPIO can now depend on GPIOLIB to allow removal of this option.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>

Add SPI driver for NVIDIA's Tegra114 SPI controller. This controller
is different than the older SoCs SPI controller in internal design as
well as register interface.

This driver supports the:
- non DMA based transfer for smaller transfer i.e. less than FIFO depth.
- APB DMA based transfer for larger transfer i.e. more than FIFO depth.
- Clock gating through runtime PM callbacks.
- registration through DT only.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

This adds support for the mostly register-compatible SPICTRL cores from the
GRLIB VHDL IP core library from Aeroflex Gaisler. They are normally running on
SPARC. A different entry in of_fsl_spi_match matches this core and indicates a
different hardware type that is used to set up different function pointers and
special cases.

The GRLIB core operates in cpu mode. The number of bits per word might be
limited. There might be native chipselects selected via a slave select
register. These differences to the FSL type cores, if present, are indicated by
a capabilities register. Other register and function differences exists but are
not relevant to the driver.
Acked-by: Anton Vorontsov <anton@enomsg.org>
Signed-off-by: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

This makes the spi-fsl-spi driver usable in CPU mode outside of an FSL_SOC and
even an powerpc environment by moving CPM mode functionality to a separate file
that is only compiled and linked in an FSL_SOC environment and adding some
ifdefs to hide types and functions or provide alternatives.

For devicetree probing a "clock-frequency" property is used for clock frequency
instead of calls to FSL_SOC-specific functions.
Acked-by: Anton Vorontsov <anton@enomsg.org>
Signed-off-by: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

With this patch an allmodconfig finally builds on s390 again.

Fixes these build errors:

ERROR: "devm_request_threaded_irq" [drivers/spi/spi-altera.ko] undefined!
ERROR: "devm_request_threaded_irq" [drivers/media/platform/sh_veu.ko] undefined!
ERROR: "devm_request_threaded_irq" [drivers/dma/dw_dmac.ko] undefined!
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>

The BCM2835 contains two forms of SPI master controller (one known
simply as SPI0, and the other known as the "Universal SPI Master", in
the auxilliary block) and one form of SPI slave controller. This patch
adds support for the SPI0 controller.

This driver is taken from Chris Boot's repository at
git://github.com/bootc/linux.git rpi-linear
as of commit 6de2905 "spi-bcm2708: fix printf with spurious %s".
In the first SPI-related commit there, Chris wrote:

Thanks to csoutreach / A Robinson for his driver which I used as an
inspiration. You can find his version here:
http://piface.openlx.org.uk/raspberry-pi-spi-kernel-driver-available-for



Changes made during upstreaming:
* Renamed bcm2708 to bcm2835 as per upstream naming for this SoC.
* Removed support for brcm,realtime property.
* Increased transfer timeout to 30 seconds.
* Return IRQ_NONE from the IRQ handler if no interrupt was handled.
* Disable TA (Transfer Active) and clear FIFOs on a transfer timeout.
* Wrote device tree binding documentation.
* Request unnamed clock rather than "sys_pclk"; the DT will provide the
  correct clock.
* Assume that tfr->speed_hz and tfr->bits_per_word are always set in
  bcm2835_spi_start_transfer(), bcm2835_spi_transfer_one(), so no need
  to check spi->speed_hz or tft->bits_per_word.
* Re-ordered probe() to remove the need for temporary variables.
* Call clk_disable_unprepare() rather than just clk_unprepare() on probe()
  failure.
* Don't use devm_request_irq(), to ensure that the IRQ doesn't fire after
  we've torn down the device, but not unhooked the IRQ.
* Moved probe()'s call to clk_prepare_enable() so we can be sure the clock
  is enabled if the IRQ handler fires immediately.
* Remove redundant checks from bcm2835_spi_check_transfer() and
  bcm2835_spi_setup().
* Re-ordered IRQ handler to check for RXR before DONE. Added comments to
  ISR.
* Removed empty prepare/unprepare implementations.
* Removed use of devinit/devexit.
* Added BCM2835_ prefix to defines.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Intel Lynxpoint PCH Low Power Subsystem has two general purpose SPI
controllers that are LPSS_SSP compatible. These controllers are enumerated
from ACPI namespace with ACPI IDs INT33C0 and INT33C1.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Lu Cao <lucao@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

To be able to use DMA with this driver on non-PXA platforms we implement
support for the generic DMA engine API. This lets user to use different DMA
engines with little or no modification to the driver.

Request lines and channel numbers can be passed to the driver from the
platform specific data.

The DMA engine implementation will be selected by default even on PXA
platform. User can select the legacy DMA API by enabling Kconfig option
CONFIG_SPI_PXA2XX_PXADMA.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Lu Cao <lucao@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

The PXA SPI driver uses PXA platform specific private DMA implementation
which does not work on non-PXA platforms. In order to use this driver on
other platforms we break out the private DMA implementation into a separate
file that gets compiled only when CONFIG_SPI_PXA2XX_PXADMA is set. The DMA
functions are stubbed out if there is no DMA implementation selected (i.e
we are building on non-PXA platform).

While we are there we can kill the dummy DMA bits in pxa2xx_spi.h as they
are not needed anymore for CE4100.

Once this is done we can add the generic DMA engine support to the driver
that allows usage of any DMA controller that implements DMA engine API.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Lu Cao <lucao@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

We are going to use it on 64-bit kernel on Intel Lynxpoint so make sure we
can build it into such kernel.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

The CONFIG_EXPERIMENTAL config item has not carried much meaning for a
while now and is almost always enabled by default. As agreed during the
Linux kernel summit, remove it from any "depends on" lines in Kconfigs.

CC: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

The MSIOF hardware block is used in the SH Mobile series as well, so we
add it here.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

This driver is obsolete and can't even be built anymore since the
platform it depends has been removed.

The STMP series is completely covered by the MXS platform these days, so
spi-mxs can be used instead.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

This patch add new driver for CLPS711X SPI master controller.
Due to platform limitations driver supports only 8 bit transfer mode.
Chip select control is handled via GPIO.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

NVIDIA's Tegra20 have the SPI (SFLASH) controller to
interface with spi flash device which is used for system
boot. Add the spi driver for this controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

The current SPI driver has many issues. Examples are:

* Segfaulting on most transfers due to expecting all transfers to have
  both RX and TX buffers.
* Hanging on TX transfers since the whole driver flow is driven by RX
  DMA completion, but the HW is only told to enable RX for RX transfers.
* Use of clk_disable_unprepare() from atomic context.
* Once those and other minor issues are fixed, the driver still doesn't
  actually work.
* The driver also implements a deprecated API to the SPI core.

For this reason, simply remove the driver completely. This has two
advantages:

1) This will remove the last use of Tegra's <mach/dma.h>, which will
   allow that file to be removed, which is required for single zImage
   work.

2) The downstream driver is significaly different from the current
   code. I believe a patch to re-add the downstream driver (with
   appropriate cleanup) will be much simpler to review if it's a new
   file rather than randomly interspered with essentially unrelated
   existing code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Remove the support code which uses the legacy APB DMA driver
for accessing the SPI FIFO.
The driver will use the dmaengine based APB DMA driver for
accessing reqding/writing to SPI FIFO.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>

Add the driver, link it into the kbuild system and provide device tree
binding documentation.
Signed-off-by: David Daney <david.daney@cavium.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: http://patchwork.linux-mips.org/patch/4292/

Signed-off-by: John Crispin <blogic@openwrt.org>

This driver adds support for NXP SC18IS602/603 I2C to SPI bus bridge.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

This is slightly reworked version of the SPI driver.
Support for DT has been added and it's been converted
to queued API.

Based on previous attempt by:
Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

The external bus unit (EBU) found on the FALCON SoC has spi emulation that is
designed for serial flash access. This driver has only been tested with m25p80
type chips. The hardware has no support for other types of spi peripherals.
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: spi-devel-general@lists.sourceforge.net
Cc: linux-mips@linux-mips.org
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Patchwork: https://patchwork.linux-mips.org/patch/3844/

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

This patch adds support for the I2C-SPI bridge which can be found on the Analog
Devices AD-FMCOMMS1-EBZ board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

The Coldfire 5251/5253 have a QSPI controller.  Enable selection of the
coldfire-qspi driver if the M525x is selected.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

Use the dmaengine based Tegra APB DMA driver for
data transfer between SPI FIFO and memory in
place of legacy Tegra APB DMA.

The new driver is selected if legacy driver is not
selected and new DMA driver is enabled through config
file.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

This controller is only for blackfin 5xx soc, so rename it to BFIN5XX
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Newer SoCs from the S3C24XX line, namely S3C2416/2443/2450 contain
hsspi-controllers compatible with the s3c64xx type.

The previous patches enabled platform support for it, so make the
driver also usable for the S3C24xx architecture.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

This patch adds support for the SPI controller found on the Broadcom BCM63xx
SoCs.
Signed-off-by: Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features:
* Master and slave modes
* 8-/12-/16-/32-bit data unit
* 256 bytes receive data FIFO and 256 bytes transmit data FIFO
* Multi-unit frame
* Configurable SPI_EN (chip select pin) active state
* Configurable SPI_CLK polarity
* Configurable SPI_CLK phase
* Configurable MSB/LSB first
Signed-off-by: Zhiwu Song <zhiwu.song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

They are all defined in an if SPI_MASTER ... endif block.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>