1. 05 Jun, 2017 5 commits
  2. 04 Jun, 2017 2 commits
    • Liam McBirnie's avatar
      ip6_tunnel: fix traffic class routing for tunnels · 5f733ee6
      Liam McBirnie authored
      ip6_route_output() requires that the flowlabel contains the traffic
      class for policy routing.
      
      Commit 0e9a7095 ("ip6_tunnel, ip6_gre: fix setting of DSCP on
      encapsulated packets") removed the code which previously added the
      traffic class to the flowlabel.
      
      The traffic class is added here because only route lookup needs the
      flowlabel to contain the traffic class.
      
      Fixes: 0e9a7095 ("ip6_tunnel, ip6_gre: fix setting of DSCP on encapsulated packets")
      Signed-off-by: default avatarLiam McBirnie <liam.mcbirnie@boeing.com>
      Acked-by: default avatarPeter Dawson <peter.a.dawson@boeing.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5f733ee6
    • Timur Tabi's avatar
      net: qcom/emac: do not use hardware mdio automatic polling · 24609669
      Timur Tabi authored
      Use software polling (PHY_POLL) to check for link state changes instead
      of relying on the EMAC's hardware polling feature.  Some PHY drivers
      are unable to get a functioning link because the HW polling is not
      robust enough.
      
      The EMAC is able to poll the PHY on the MDIO bus looking for link state
      changes (via the Link Status bit in the Status Register at address 0x1).
      When the link state changes, the EMAC triggers an interrupt and tells the
      driver what the new state is.  The feature eliminates the need for
      software to poll the MDIO bus.
      
      Unfortunately, this feature is incompatible with phylib, because it
      ignores everything that the PHY core and PHY drivers are trying to do.
      In particular:
      
      1. It assumes a compatible register set, so PHYs with different registers
         may not work.
      
      2. It doesn't allow for hardware errata that have work-arounds implemented
         in the PHY driver.
      
      3. It doesn't support multiple register pages. If the PHY core switches
         the register set to another page, the EMAC won't know the page has
         changed and will still attempt to read the same PHY register.
      
      4. It only checks the copper side of the link, not the SGMII side.  Some
         PHY drivers (e.g. at803x) may also check the SGMII side, and
         report the link as not ready during autonegotiation if the SGMII link
         is still down.  Phylib then waits for another interrupt to query
         the PHY again, but the EMAC won't send another interrupt because it
         thinks the link is up.
      
      Cc: stable@vger.kernel.org # 4.11.x
      Tested-by: default avatarManoj Iyer <manoj.iyer@canonical.com>
      Signed-off-by: default avatarTimur Tabi <timur@codeaurora.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      24609669
  3. 02 Jun, 2017 11 commits
  4. 01 Jun, 2017 11 commits
  5. 31 May, 2017 6 commits
  6. 30 May, 2017 5 commits