- 11 Aug, 2023 1 commit
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Dmitry Baryshkov authored
The conversion commit 7559e757 ("phy: Explicitly include correct DT includes") misses offsets configuration for sm8150 (most likely it was developed separately from the series adding HS G4 support and was not adapted for the sm8150/sm8250 configuration split). Add missing offsets to sm8150_ufsphy_cfg. Fixes: 7559e757 ("phy: Explicitly include correct DT includes") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230731111009.3998089-1-dmitry.baryshkov@linaro.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 26 Jul, 2023 1 commit
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Geert Uytterhoeven authored
The various StarFive PHYs are only present on StarFive SoCs. Hence add a dependency on ARCH_STARFIVE, to prevent asking the user about these drivers when configuring a kernel without StarFive SoC support. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/12097f6107a18e2f7cfb80f47ac7b27808e062c4.1690300076.git.geert+renesas@glider.beSigned-off-by:
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- 25 Jul, 2023 1 commit
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Vinod Koul authored
the startfive phy drivers use devm_platform_ioremap_resource() which on some archs (s390) is not present. So make the drivers depend on HAS_IOMEM Fixes: f8aa6608 ("phy: starfive: Add mipi dphy rx support") Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307250509.oeudxG28-lkp@intel.com/Reviewed-by:
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- 24 Jul, 2023 8 commits
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Dmitry Baryshkov authored
Add separate device entry for Combo USB+DP QMP PHY on sc7280 platform. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
In order to support newer style bindings for combo PHYs, populate offsets for all Combo QMP PHY configurations. Reviewed-by:
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Dmitry Baryshkov authored
For the existing PHYs for new binding we are going to drop ref_clk_src clock and always use ref clock. Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional() when new bindings are used and devm_clk_bulk_get_all() when legacy bindings are in place. Signed-off-by:
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Dmitry Baryshkov authored
Migrate legacy bindings (described in qcom,sc7180-qmp-usb3-dp-phy.yaml) to qcom,sc8280xp-qmp-usb43dp-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Yang Li authored
./drivers/phy/tegra/xusb.c: linux/platform_device.h is included more than once. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5930Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Acked-by:
Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230719003614.5506-1-yang.lee@linux.alibaba.comSigned-off-by:
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Changhuang Liang authored
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by:
Minda Chen <minda.chen@starfivetech.com> Link: https://lore.kernel.org/r/20230718070803.16660-3-changhuang.liang@starfivetech.comSigned-off-by:
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Changhuang Liang authored
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718070803.16660-2-changhuang.liang@starfivetech.comSigned-off-by:
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Dan Carpenter authored
This is using the wrong pointer, "phy->regs" vs "phy->phy". Fixes: fd097f48 ("phy: starfive: Add JH7110 PCIE 2.0 PHY driver") Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/3cc81f2a-efd7-4ef7-ae6b-e38c91efe153@moroto.mountainSigned-off-by:
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- 18 Jul, 2023 3 commits
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Sebastian Reichel authored
When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230717173512.65169-2-sebastian.reichel@collabora.comSigned-off-by:
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Mrinmay Sarkar authored
Add support for dual and four lane PHY found on sa8755p platform. Signed-off-by:
Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689311319-22054-5-git-send-email-quic_msarkar@quicinc.comSigned-off-by:
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Mrinmay Sarkar authored
Add devicetree YAML binding for Qualcomm QMP PCIe PHY for SA8775p platform. Signed-off-by:
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- 17 Jul, 2023 1 commit
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Rob Herring authored
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.orgSigned-off-by:
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- 14 Jul, 2023 1 commit
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Andrew Davis authored
If the parent node is not a syscon type, then fallback and check if we can get a regmap from our own node. This no longer forces us to make the parent of this node a syscon node when that might not be appropriate. Signed-off-by:
Andrew Davis <afd@ti.com> Reviewed-by:
Roger Quadros <rogerq@ti.com> Reviewed-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20230713200957.134480-1-afd@ti.comSigned-off-by:
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- 12 Jul, 2023 24 commits
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Sean Anderson authored
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by:
Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.comSigned-off-by:
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Dmitry Baryshkov authored
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Reviewed-by:
Bjorn Andersson <andersson@kernel.org> Signed-off-by:
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Dmitry Baryshkov authored
Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml) to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by:
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Minda Chen authored
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-5-minda.chen@starfivetech.comSigned-off-by:
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Minda Chen authored
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by:
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Minda Chen authored
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by:
Hal Feng <hal.feng@starfivetech.com> Reviewed-by:
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Minda Chen authored
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by:
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Marcin Wierzbicki authored
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by:
Bartosz Wawrzyniak <bwawrzyn@cisco.com> Signed-off-by:
Marcin Wierzbicki <mawierzb@cisco.com> Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.comSigned-off-by:
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Alex Bee authored
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by:
Alex Bee <knaerzche@gmail.com> Signed-off-by:
Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.seSigned-off-by:
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Huicong Xu authored
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by:
Huicong Xu <xhc@rock-chips.com> Signed-off-by:
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Jonas Karlman authored
inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a11 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by:
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Jonas Karlman authored
no_c is not used in any calculation, lets remove it. Signed-off-by:
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Zheng Yang authored
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found in the pre pll config table when the fractal divider is used. This can prevent proper power_on because a tmdsclock for the new rate is not found in the pre pll config table. Fix this by saving and returning a rounded pixel rate that exist in the pre pll config table. Fixes: 53706a11 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by:
Zheng Yang <zhengyang@rock-chips.com> Signed-off-by:
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Jonas Karlman authored
inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro when configuring vco_div_5 on RK3328. Fix this by using correct vco_div_5 macro for RK3328. Fixes: 53706a11 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by:
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Dmitry Baryshkov authored
Extact qmp_combo_configure_dp_clocks(), a common function to setup PHY clocks depending on the selected link rate. Signed-off-by:
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Dmitry Baryshkov authored
The only difference between qmp_v6_dp_aux_init() and qmp_v4_dp_aux_init() is the address of COM_BIAS_EN_CLKBUFLR_EN register. Move it to register layout and drop the duplicate function. Signed-off-by:
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Dmitry Baryshkov authored
The functions qmp_v5_configure_dp_phy() and qmp_v6_configure_dp_phy() are now copies of qmp_v4_configure_dp_phy(). Drop them and use the v4 function in all the cases. Signed-off-by:
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Dmitry Baryshkov authored
Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN registers. This will allow us to unify qmp_v[456]_configure_dp_phy() functions in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
Instead of passing additional registers to qmp_combo_configure_dp_swing(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by:
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Dmitry Baryshkov authored
Instead of passing additional registers to qmp_v456_configure_dp_phy(), reuse qphy_reg_layout and add those registers to register layout maps. Signed-off-by:
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Dmitry Baryshkov authored
It seems the commit a2e927b0 ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") contained a typo for selecting bias0_en values. First, bias0_en and bias1_en are expected to be symmetrical, and then the vendor driver also uses `flipped : 0x3E : 0x15` statement for bias0_en. Correct bias0_en programming to follow this. Fixes: 49742e9e ("phy: qcom-qmp-combo: Add support for SM8550") Fixes: a2e927b0 ("phy: qcom-qmp-combo: Add sc8280xp USB/DP combo phys") Signed-off-by:
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Piyush Mehta authored
Enabling clock for all the lanes consumes power even PHY is active or inactive. To resolve this, enable/disable clocks in phy_init/phy_exit. By default clock is disabled for all the lanes. Whenever phy_init called from USB, SATA, or display driver, etc. It enabled the required clock for requested lane. On phy_exit cycle, it disabled clock for the active PHYs. During the suspend/resume cycle, each USB/ SATA/ display driver called phy_exit/phy_init individually. It disabled clock on exit, and enabled on initialization for the active PHYs. Signed-off-by:
Piyush Mehta <piyush.mehta@amd.com> Link: https://lore.kernel.org/r/20230613140250.3018947-3-piyush.mehta@amd.comSigned-off-by:
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Piyush Mehta authored
Added Runtime power management support to the xilinx phy driver and using DEFINE_RUNTIME_DEV_PM_OPS new macros allows the compiler to remove the unused dev_pm_ops structure and related functions if !CONFIG_PM without the need to mark the functions __maybe_unused. Signed-off-by:
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AngeloGioacchino Del Regno authored
All of the entries do fit in a maximum of 82 columns, which is acceptable. While at it, also remove the useless comma on the last entry and add the usual sentinel comment. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230525115258.90091-4-angelogioacchino.delregno@collabora.comSigned-off-by:
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