- 27 Jan, 2015 40 commits
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Damien Lespiau authored
crtc->base.primary->fb was used everywhere. Use fb to temporarily point there and don't forget to assign fb to its final destination at the end. v2: Rebase on top of misc changes (mask of DSPSURF, PAGE_ALIGN) Reviewed-By:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Damien Lespiau authored
If we need to change the fb height constraints, it sounds like a good idea to have to do it in one place only. v2: v2: Rebase on top of Ander's "Make intel_crtc->config a pointer" Reviewed-By: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v1) Signed-off-by:
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Damien Lespiau authored
Rather than having "tiled" meaning "is it X-tiled?" convert the field to explicitely store the tiling mode. The code doesn't have to change much as 1 is conveniently I915_TILING_X. This is to accommodate future changes around tiling modes and scannout buffers. v2: Rebase on top of Ander's "Make intel_crtc->config a pointer" Reviewed-By: Tvrtko Ursulin <tvrtko.ursulin@intel.com> (v1) Signed-off-by:
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Zhe Wang authored
Enable coarse power gating for Gen9. This feature allows render and media engine to enter RC6 independently. Policies are configured together with RC6. This feature will only be enabled when RC6 is enabled. v2: Rebase after Chris'/Mika's forcewake change (Damien) Reviewed-by:
Zhe Wang <zhe1.wang@intel.com> Signed-off-by:
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Damien Lespiau authored
v2: Use the new function, gen6_init_rps_frequencies() (Damien) Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (v1) Signed-off-by:
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Jesse Barnes authored
Per latest PM programming guide. v2: the wrong flavour of the function updating the ring frequency was called, leading to dead locks (Tvrtko) v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien) Signed-off-by:Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> [danvet: Fixup conflicts with Mika's forcewake refactor.] Signed-off-by:
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Satheeshakrishna M authored
Adding new power doamins for AUX controllers v2: Added new power domains in power_domain_str per Imre's comment v3: Added AUX power domains to older platforms v4: Rebase on top of POWER_DOMAIN_PLLS. v5: Modified to address review comments from Imre Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3) Signed-off-by:
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Mika Kuoppala authored
There are multiple forcewake domains in newer architectures. Rename 'i915_gen6_forcewake_count_info' debugfs entry to 'i915_forcewake_domains' to reflect this. Signed-off-by:
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Mika Kuoppala authored
Make the domains and domain identifiers enums. To emphasize the difference in order to avoid mistakes. v2: s/fw_domain/forcewake_domain (Jani) v3: rebase Suggested-by:
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Mika Kuoppala authored
We have multiple forcewake domains now on recent gens. Change the function naming to reflect this. v2: More verbose names (Chris) v3: Rebase v4: Rebase v5: Add documentation for forcewake_get/put Signed-off-by:
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Mika Kuoppala authored
These two were using a fw dance logic where posting read was done after both domain bit were set. When in other gens, the posting read is done immediately after setting the forcewake bit for each domain. Now bring these in line with other gens. Signed-off-by:
Deepak S <deepak.s@linux.intel.com> Signed-off-by:
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Mika Kuoppala authored
As we now have forcewake domains, take advantage of it by putting the differences in gen fw handling in data rather than in code. In past we have opencoded this quite extensively as the fw handling is in the fast path. There has also been a lot of cargo-culted copy'n'pasting from older gens to newer ones. Now when the releasing of the forcewake is done by deferred timer, it gives chance to consolidate more. Due to the frequency of actual hw access being significantly less. Take advantage of this and generalize the fw handling code as much as possible. But we still aim to keep the forcewake sequence particularities for each gen intact. So the access pattern to fw engines should remain the same. v2: - s/old_ack/clear_ack (Chris) - s/post_read/posting_read (Chris) - less polite commit msg (Chris) v3: - rebase - check and clear wake_count in init v4: - fix posting reads for gen8 (PRTS) Signed-off-by: -
Chris Wilson authored
Introduce a structure to track the individual forcewake domains and use that to eliminate duplicate logic. v2: - Rebase on latest dinq (Mika) - for_each_fw_domain macro (Mika) - Handle reset atomically, keeping the timer running (Mika) - for_each_fw_domain parameter ordering (Chris) - defer timer on new register access (Mika) v3: - Fix forcewake_reset/get race by waiting pending timers v4: - cond_resched and verbose warning on timer deletion (Chris) - need to run pending timers manually on reset Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) Signed-off-by: -
Chris Wilson authored
With gen < 6 we don't need to take uncore lock as we don't have anything to protect from concurrent access. v2: rebase and account for gen9 changes Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) Signed-off-by:
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Chris Wilson authored
On user forcewake access, assert that runtime pm reference is held. Fix and cleanup the callsites accordingly. v2: Remove intel_runtime_pm_get() rebasehap (Deepak) v3: use drivers own runtime state tracking as pm_runtime_active() will return wrong results when we are in resume callchain (Mika) Signed-off-by:Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Chris Wilson authored
Calling intel_runtime_pm_put() is illegal from a soft-irq context, so revert the crude hack commit aa0b3b5b Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Tue Apr 1 14:55:07 2014 -0300 drm/i915: don't schedule force_wake_timer at gen6_read and apply the single line corrective instead. v2: assert forcewake is off after the forcewake_reset (Paulo) References: https://bugs.freedesktop.org/show_bug.cgi?id=80913 Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Nick Hoath authored
Move all remaining elements that were unique to execlists queue items in to the associated request. Issue: VIZ-4274 v2: Rebase. Fixed issue of overzealous freeing of request. v3: Removed re-addition of cleanup work queue (found by Daniel Vetter) v4: Rebase. v5: Actual removal of intel_ctx_submit_request. Update both tail and postfix pointer in __i915_add_request (found by Thomas Daniel) v6: Removed unrelated changes Signed-off-by:
Nick Hoath <nicholas.hoath@intel.com> Reviewed-by:
Thomas Daniel <thomas.daniel@intel.com> [danvet: Reformat comment with strange linebreaks.] Signed-off-by:
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Nick Hoath authored
The first pass implementation of execlists required a backpointer to the context to be held in the intel_ringbuffer. However the context pointer is available higher in the call stack. Remove the backpointer from the ring buffer structure and instead pass it down through the call stack. v2: Integrate this changeset with the removal of duplicate request/execlist queue item members. v3: Rebase v4: Rebase. Remove passing of context when the request is passed. Signed-off-by:
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Nick Hoath authored
Where there were duplicate variables for the tail, context and ring (engine) in the gem request and the execlist queue item, use the one from the request and remove the duplicate from the execlist queue item. Issue: VIZ-4274 v1: Rebase v2: Fixed build issues. Keep separate postfix & tail pointers as these are used in different ways. Reinserted missing full tail pointer update. Signed-off-by:
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Nick Hoath authored
Add a reference and pointer from the execlist queue item to the associated gem request. For execlist requests that don't have a request, create one as a placeholder. Issue: VIZ-4274 v1: Rebase after upstream of "Replace seqno values with request structures" patchset. Signed-off-by:
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Ander Conselvan de Oliveira authored
So that atomic operations will reference the right crtc state. Signed-off-by:
Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Ander Conselvan de Oliveira authored
The previous patch changed the config field in intel_crtc to a pointer, but to keep the mechanical changes (done with spatch) separate from the new code, the pointer was made to point to a new _config field with type struct intel_crtc_state added to that struct. This patch improves that code by getting rid of that field, allocating a state struct in intel_crtc_init() a keeping it properly updated when a mode set happens. v2: Manual changes split from previous patch. (Matt) Don't leak the current state when the crtc is destroyed (Matt) Signed-off-by: -
Ander Conselvan de Oliveira authored
To match the semantics of drm_crtc->state, which this will eventually become. The allocation of the memory for config will be fixed in a followup patch. By adding the extra _config field to intel_crtc it was possible to generate this entire patch with the cocci script below. @@ @@ struct intel_crtc { ... -struct intel_crtc_state config; +struct intel_crtc_state _config; +struct intel_crtc_state *config; ... } @@ struct intel_crtc *crtc; @@ -memset(&crtc->config, 0, sizeof(crtc->config)); +memset(crtc->config, 0, sizeof(*crtc->config)); @@ @@ __intel_set_mode(...) { <... -to_intel_crtc(crtc)->config = *pipe_config; +(*(to_intel_crtc(crtc)->config)) = *pipe_config; ...> } @@ @@ intel_crtc_init(...) { ... WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); +intel_crtc->config = &intel_crtc->_config; return; ... } @@ struct intel_crtc *crtc; @@ -&crtc->config +crtc->config @@ struct intel_crtc *crtc; identifier member; @@ -crtc->config.member +crtc->config->member @@ expression E; @@ -&(to_intel_crtc(E)->config) +to_intel_crtc(E)->config @@ expression E; identifier member; @@ -to_intel_crtc(E)->config.member +to_intel_crtc(E)->config->member v2: Clarify manual changes by splitting them into another patch. (Matt) Improve cocci script to generate even more of the changes. (Ander) Signed-off-by: -
Ander Conselvan de Oliveira authored
In functions that define a local pipe_config variable to point to crtc->config, replace remaining references to crtc->config with the local variable. This makes the code more consistent and easier to change in an automated manner. Signed-off-by:
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Ander Conselvan de Oliveira authored
This reduces the number of direct users of crtc->new_config, opening up the possibilty of removing it altogether. Signed-off-by:
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Ander Conselvan de Oliveira authored
And get rid of the duplicate mode structures. This patch was generated with the following semantic patch: @@ @@ struct intel_crtc_state { +struct drm_crtc_state base; + ... -struct drm_display_mode requested_mode; -struct drm_display_mode adjusted_mode; ... } @@ struct intel_crtc_state *state; @@ -state->adjusted_mode +state->base.adjusted_mode @@ struct intel_crtc_state *state; @@ -state->requested_mode +state->base.mode @@ struct intel_crtc_state state; @@ -state.adjusted_mode +state.base.adjusted_mode @@ struct intel_crtc_state state; @@ -state.requested_mode +state.base.mode @@ struct drm_crtc *crtc; @@ -to_intel_crtc(crtc)->config.adjusted_mode +to_intel_crtc(crtc)->config.base.adjusted_mode @@ identifier member; expression E; @@ -PIPE_CONF_CHECK_FLAGS(adjusted_mode.member, E); +PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.member, E); @@ identifier member; @@ -PIPE_CONF_CHECK_I(adjusted_mode.member); +PIPE_CONF_CHECK_I(base.adjusted_mode.member); @@ identifier member; @@ -PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.member); +PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.member); v2: Completely generate the patch with cocci. (Ander) Signed-off-by: -
Ander Conselvan de Oliveira authored
The objective is to make this structure usable with the atomic helpers, so let's start with the rename. Patch generated with coccinelle: @@ @@ -struct intel_crtc_config { +struct intel_crtc_state { ... } @@ @@ -struct intel_crtc_config +struct intel_crtc_state v2: Completely generate the patch with cocci. (Ander) Signed-off-by: -
Vandana Kannan authored
Earlier, DRRS structures were specific to eDP (used only in intel_dp). Since DRRS can be extended to other internal display types (if the panel supports multiple RR), modifying structures to be part of drm_i915_private and have a provision to add display related structs like intel_dp. Also, aligning with frontbuffer tracking mechanism, the new structure contains data for busy frontbuffer bits. Signed-off-by:
Vandana Kannan <vandana.kannan@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
On VLV/CHV the rc6 residency calculations read a second register to determine the actual units used for the residency value. The variable name 'reg' where that register value is stored shadows the function argument 'reg'. That can easily leave the reader utterly confused, so rename the internal variable to 'clk_reg'. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Ville Syrjälä authored
We don't register the rc6p and rc6pp sysfs files on VLV, so there's no point in having any VLV checks in them. Drop the checks. Signed-off-by:
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Ville Syrjälä authored
The performance regression from the CHV RC6 EI->TO change is now fixed so re-enable TO mode for better RC6 resicency. This reverts commit e85a5c79. Signed-off-by:
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Ville Syrjälä authored
CherryViewA0_iGfx_BIOS_DRIVER_PUNIT_spec_y14w28d5 tells us not to enable the RP down timeout interrupt, and says that the timeout value is hence not used. We do enable that interrupt currently though, so leaving the timeout as 0 results in very poor performance as the GPU frequency keeps dropping constantly. So just program the register with the recommended value. Leaving the interrupt enabled doesn't seem to do any harm so far. So I've decided to leave it on for now, just to avoid making CHV a special case. This fixes the performance regression from: commit 5a0afd4b Author: Deepak S <deepak.s@linux.intel.com> Date: Sat Dec 13 11:43:27 2014 +0530 drm/i915/chv: Use timeout mode for RC6 on chv Cc: Deepak S <deepak.s@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
We use decimal for all the other RP magic values, so change GEN6_RP_DOWN_TIMEOUT to decimal as well. Also change the order of the register writes to match the BIOS spec for easier verification. Signed-off-by:
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Ville Syrjälä authored
Follow the sequence in the BIOS spec and clear the RC_CONTROL register before changing any of the other RC6/RP registers. Signed-off-by:
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Deepak S authored
Use new Sideband offset to read max/min/gaur freq based on the SKU it is running on. Based on the Number of EU, we read different bits to identify the max frequencies at which system can run. v2: reuse mask definitions & INTEL_INFO() to get device info (Ville) v3: add break in switch conditions (Ville) Signed-off-by:
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Deepak S authored
Looks like latest BSW/CHV production system has sideband address > 128. Use u32 data types to cover new offset/address range :) Signed-off-by:
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Deepak S authored
Starting with Cherryview, devices may have a varying number of EU for a given ID due to creative fusing. Punit support different frequency for different fuse data. We use this patch to help get total eu enabled and read the right offset to get RP0 Based upon a patch from Jeff, but reworked to only store eu_total and avoid sending info to userspace v2: Format register definitions (Jani) Signed-off-by:
Jeff McGee <jeff.mcgee@intel.com> Reviewed-by:
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Matt Roper authored
When we transitioned to the atomic plane helpers in commit: commit ea2c67bb Author: Matt Roper <matthew.d.roper@intel.com> Date: Tue Dec 23 10:41:52 2014 -0800 drm/i915: Move to atomic plane helpers (v9) one of the changes was to call intel_plane_destroy_state() while tearing down a plane to prevent leaks when unloading the driver. That made sense when the patches were first written, but before they were merged, commit 3009c037 Author: Thierry Reding <treding@nvidia.com> Date: Tue Nov 25 12:09:49 2014 +0100 drm: Free atomic state during cleanup had already landed, which made this the responsibility of the DRM core. The result was that we were kfree()'ing the state twice, and also possibly double-unref'ing a framebuffer, leading to memory corruption when the driver was unloaded. The fix is to simply not try to cleanup the state in the i915 teardown code now that the core handles this for us. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88433 Testcase: igt/drv_module_reload Root-cause-analysis-by:Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Matt Roper authored
The rotation property is shared by multiple drivers, so it makes sense to store the rotation value (for atomic-converted drivers) in the common plane state so that core code can eventually access it as well. Cc: dri-devel@lists.freedesktop.org Suggested-by:
Daniel Vetter <daniel@ffwll.ch> Reviewed-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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https://github.com/markyzq/kernel-drm-rockchipDave Airlie authored
single rockchip fix. * 'drm-next' of https://github.com/markyzq/kernel-drm-rockchip: drm/rockchip: fix dma_alloc_attrs() error check
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