- 26 Aug, 2022 1 commit
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Ville Syrjälä authored
The stuff programmed into the wm/ddb registers of planes on disabled pipes doesn't matter. So during readout just leave our software state tracking for those zeroed. This should avoid us trying too hard to clean up after whatever mess the VBIOS/GOP left in there. The actual hardware state will get cleaned up if/when we enable the pipe anyway. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5711Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220617195948.24007-1-ville.syrjala@linux.intel.comReviewed-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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- 25 Aug, 2022 11 commits
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José Roberto de Souza authored
Display version 14 also supports MBUS joining just like ADL-P and also it does not need MBUS initialization, so extending ADL-P code paths to display version 14 and higher. Bspec: 49213 Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220818234202.451742-20-radhakrishna.sripada@intel.com
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Radhakrishna Sripada authored
Meteorlake uses a similar DBUF calculations as ADL-P. Reuse the call flow for meteorlake. Bspec: 49255 Original Author: Caz Yokoyama Reviewed-by:
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Radhakrishna Sripada authored
Like ADL_P, Meteorlake has different memory characteristics from past platforms. Update the values used by our memory bandwidth calculations accordingly. Bspec: 64631 Reviewed-by:
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Radhakrishna Sripada authored
Since Xe LPD+, Memory latency data are in LATENCY_LPX_LPY registers instead of GT driver mailbox. v2: Use the extracted wm latency adjustment function(Matt) v3: Use Odd/even for Latency fields(MattR) Bspec: 64608 Cc: Matt Roper <matthew.d.roper@intel.com> Original Author: Caz Yokoyama Signed-off-by:
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Radhakrishna Sripada authored
Watermark latency is adjusted in cases when latency is 0us for level greater than 1, the subsequent levels are disabled. Extract this logic into its own function. v2: Pass dev_priv to the extracted function(MattR) Suggested-by:
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Clint Taylor authored
MTL has a fixed rawclk of 38400Khz. Register does not need to be reprogrammed. Bspec: 49304 Reviewed-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
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Radhakrishna Sripada authored
The initialization sequence for Meteorlake reuses the sequence for icelake for most parts. Some changes viz. reset PICA handshake are added. Bspec: 49189 Reviewed-by:
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Imre Deak authored
Add the proper VBT port,AUX_CH -> i915 port,AUX_CH mapping which just follows the ADL_P one. Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Radhakrishna Sripada authored
Add support for Meteorpoint(MTP) PCH used with Meteorlake. Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
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Diego Santa Cruz authored
The quirk added in upstream commit 90c3e219 ("drm/i915/glk: Add Quirk for GLK NUC HDMI port issues.") is also required on the ECS Liva Q2. Note: Would be nicer to figure out the extra delay required for the retimer without quirks, however don't know how to check for that. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1326Signed-off-by:
Diego Santa Cruz <Diego.SantaCruz@spinetix.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220616124137.3184371-1-jani.nikula@intel.com
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Łukasz Bartosik authored
Asus chromebook CX550 crashes during boot on v5.17-rc1 kernel. The root cause is null pointer defeference of bi_next in tgl_get_bw_info() in drivers/gpu/drm/i915/display/intel_bw.c. BUG: kernel NULL pointer dereference, address: 000000000000002e PGD 0 P4D 0 Oops: 0002 [#1] PREEMPT SMP NOPTI CPU: 0 PID: 1 Comm: swapper/0 Tainted: G U 5.17.0-rc1 Hardware name: Google Delbin/Delbin, BIOS Google_Delbin.13672.156.3 05/14/2021 RIP: 0010:tgl_get_bw_info+0x2de/0x510 ... [ 2.554467] Call Trace: [ 2.554467] <TASK> [ 2.554467] intel_bw_init_hw+0x14a/0x434 [ 2.554467] ? _printk+0x59/0x73 [ 2.554467] ? _dev_err+0x77/0x91 [ 2.554467] i915_driver_hw_probe+0x329/0x33e [ 2.554467] i915_driver_probe+0x4c8/0x638 [ 2.554467] i915_pci_probe+0xf8/0x14e [ 2.554467] ? _raw_spin_unlock_irqrestore+0x12/0x2c [ 2.554467] pci_device_probe+0xaa/0x142 [ 2.554467] really_probe+0x13f/0x2f4 [ 2.554467] __driver_probe_device+0x9e/0xd3 [ 2.554467] driver_probe_device+0x24/0x7c [ 2.554467] __driver_attach+0xba/0xcf [ 2.554467] ? driver_attach+0x1f/0x1f [ 2.554467] bus_for_each_dev+0x8c/0xc0 [ 2.554467] bus_add_driver+0x11b/0x1f7 [ 2.554467] driver_register+0x60/0xea [ 2.554467] ? mipi_dsi_bus_init+0x16/0x16 [ 2.554467] i915_init+0x2c/0xb9 [ 2.554467] ? mipi_dsi_bus_init+0x16/0x16 [ 2.554467] do_one_initcall+0x12e/0x2b3 [ 2.554467] do_initcall_level+0xd6/0xf3 [ 2.554467] do_initcalls+0x4e/0x79 [ 2.554467] kernel_init_freeable+0xed/0x14d [ 2.554467] ? rest_init+0xc1/0xc1 [ 2.554467] kernel_init+0x1a/0x120 [ 2.554467] ret_from_fork+0x1f/0x30 [ 2.554467] </TASK> ... Kernel panic - not syncing: Fatal exception Fixes: c64a9a7c ("drm/i915: Update memory bandwidth formulae") Signed-off-by:
Łukasz Bartosik <lb@semihalf.com> Reviewed-by:
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- 24 Aug, 2022 14 commits
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Taylor, Clinton A authored
Using the BSPEC algorithm add addition HDMI pixel clocks to the existing table. v2: remove 297000 unused entry Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> [mattrope: Fixed minor whitepsace issue flagged by checkpatch] Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. Signed-off-by:
Maarten Lankhort <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0e2646e5fdaad2785678b4f140091b3d91b97f7e.1660910433.git.jani.nikula@intel.com
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Jani Nikula authored
If it's modified runtime, it's runtime info. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. mock_gem_device() is the only one that modifies it. If that could be fixed, we wouldn't have to do this. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. mock_gem_device() is the only one that modifies it. If that could be fixed, we wouldn't have to do this. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. Curiously, the flag was never initialized statically. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. v2: Rebase on mtl fbc_mask Signed-off-by:
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Jani Nikula authored
If it's modified runtime, it's runtime info. mock_gem_device() is the only one that modifies them. If that could be fixed, we wouldn't have to do this. Signed-off-by:
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Jani Nikula authored
Add initial runtime info that we can copy to runtime info at i915 creation time. This lets us define the initial values for runtime info statically while making it possible to change them runtime. This will be the new home for the current "const" device info members that are modified runtime anyway. Signed-off-by:
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Jani Nikula authored
We'll be moving info between static and runtime info. Combine the printing functions into one to keep the output sensible and (mostly) unchanged in the process. Signed-off-by:
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- 23 Aug, 2022 2 commits
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Jouni Högander authored
Pps power hook seems to be problematic for backlight controlled via aux channel. Disable it for such cases. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3657 Cc: stable@vger.kernel.org Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Signed-off-by:
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Jani Nikula authored
Remove unused macros. If needed again, such macros belong in <linux/units.h>. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220815080907.3229449-1-jani.nikula@intel.com
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- 22 Aug, 2022 3 commits
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Vandita Kulkarni authored
DSC 1.2 is supported from MTL, hence program ICH accordingly. Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Vandita Kulkarni authored
From MTL onwards we support DSC 1.2, since there is hardcoding to minor version 1, update it. Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Arun R Murthy authored
Commit 20f85ef8 ("drm/i915/backlight: use unique backlight device names") added support for multiple backlight devices on dual panel systems, but did so with error handling on -EEXIST from backlight_device_register(). Unfortunately, that triggered a warning in dmesg all the way down from sysfs_add_file_mode_ns() and sysfs_warn_dup(). Instead of optimistically always attempting to register with the default name ("intel_backlight", which we have to retain for backward compatibility), check if a backlight device with the name exists first, and, if so, use the card and connector based name. v2: reworked on top of the patch commit 20f85ef8 ("drm/i915/backlight: use unique backlight device names") v3: fixed the ref count leak(Jani N) Fixes: 20f85ef8 ("drm/i915/backlight: use unique backlight device names") Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
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- 19 Aug, 2022 2 commits
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Ville Syrjälä authored
MTL introduces a second FBC engine. The two FBC engines can operate entirely independently, FBC A serving pipe A and FBC B serving pipe B. The one place where things might go a bit wrong is the CFB allocation from stolen. We might have to consider some change to the allocation strategy to have a better chance of both engines being able to allocate its CFB. Maybe FBC A should allocate bottom up and FBC B top down, or something? For the moment the allocation strategy is DRM_MM_INSERT_BEST for both. Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
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Jani Nikula authored
Meteorlake and newer platforms support DP 2.0. Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220817121948.180655-1-jani.nikula@intel.com
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- 18 Aug, 2022 3 commits
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Jani Nikula authored
Drop the intermediate values stored in intel_dsi and use the VBT values directly, now that they're conveniently stored in panel->vbt. Signed-off-by:
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Jani Nikula authored
The VBT dual-link DSI backlight and CABC still use ports A and C, both in Bspec and code, while display 11+ DSI only supports ports A and B. Assume port C actually means port B for display 11+ when parsing VBT. Bspec: 20154 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6476 Cc: stable@vger.kernel.org Signed-off-by:
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Jani Nikula authored
Avoid using ports that aren't initialized in case the VBT backlight or CABC ports have invalid values. This fixes a NULL pointer dereference of intel_dsi->dsi_hosts[port] in such cases. Cc: stable@vger.kernel.org Signed-off-by:
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- 17 Aug, 2022 1 commit
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Bo Liu authored
There is an unexpected word "the" in the file i915_irq.c, fix it. Signed-off-by:
Bo Liu <liubo03@inspur.com> Signed-off-by:
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- 16 Aug, 2022 1 commit
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Jani Nikula authored
Declutter i915_reg.h by splitting backlight registers to a separate file. Also include the utility pin definitions, even though they are used for non-backlight things too. Signed-off-by:
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- 15 Aug, 2022 2 commits
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Imre Deak authored
Make sure the TypeC PHY ownership flag is not getting reset during an HDMI modeset on the given port. Besides the WARN this triggered, it didn't cause other issues, since for TypeC legacy mode setting the PHY ownership flag is optional (there is no other user of the PHY besides display). Reported-and-tested-by:
Shawn C Lee <shawn.c.lee@intel.com> Signed-off-by:
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Imre Deak authored
At the moment on DG2 at least loading the DMC firmware's PIPEDMC C and D programs leads to sporadic unclaimed register accesses while programming the initial state as described by the firmware's "MMIO init" table. This will also lead to later unclaimed accesses for unrelated transcoder/pipe registers backed by the pipe C and D display power wells. Disabling the PIPEDMC clock gating during initialization - similarly to Wa_16015201720 fixed this problem in my tests. While pipe A an B requires the clock gating to be disabled all the time pipe C and D requires this only while accessing the PIPEDMC registers. Bspec: 49193 References: https://gitlab.freedesktop.org/drm/intel/-/issues/6526 References: https://gitlab.freedesktop.org/drm/intel/-/issues/6308Signed-off-by:
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