- 08 Jun, 2021 3 commits
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Jonathan Marek authored
Value was shifted in the wrong direction, resulting in the field always being zero, which is incorrect for A650. Fixes: d0bac4e9 ("drm/msm/a6xx: set ubwc config for A640 and A650") Signed-off-by:
Jonathan Marek <jonathan@marek.ca> Reviewed-by:
Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210513171431.18632-4-jonathan@marek.caSigned-off-by:
Rob Clark <robdclark@chromium.org>
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Jonathan Marek authored
Update CP_PROTECT register programming based on downstream. A6XX_PROTECT_RW is renamed to A6XX_PROTECT_NORDWR to make things aligned and also be more clear about what it does. Note that this required switching to use the CP_ALWAYS_ON_COUNTER as the GMU counter is not accessible from the cmdstream. Which also means using the CPU counter for the msm_gpu_submit_flush() tracepoint (as catapult depends on being able to compare this to the start/end values captured in cmdstream). This may need to be revisited when IFPC is enabled. Also, compared to downstream, this opens up CP_PERFCTR_CP_SEL as the userspace performance tooling (fdperf and pps-producer) expect to be able to configure the CP counters. Fixes: 4b565ca5 ("drm/msm: Add A6XX device support") Signed-off-by:
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Alexey Minnekhanov authored
Fix NULL pointer dereference caused by update_inactive() trying to list_del() an uninitialized mm_list who's prev/next pointers are NULL. Fixes: 64fcbde7 ("drm/msm: Track potentially evictable objects") Signed-off-by:
Alexey Minnekhanov <alexeymin@postmarketos.org> Link: https://lore.kernel.org/r/20210518102624.1193955-1-alexeymin@postmarketos.orgSigned-off-by:
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- 06 May, 2021 2 commits
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Kuogee Hsieh authored
Initialize audio_comp when audio starts and wait for audio_comp at dp_display_disable(). This will take care of both dongle unplugged and display off (suspend) cases. Changes in v2: -- add dp_display_signal_audio_start() Changes in v3: -- restore dp_display_handle_plugged_change() at dp_hpd_unplug_handle(). Changes in v4: -- none Signed-off-by:
Kuogee Hsieh <khsieh@codeaurora.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Tested-by:
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Kuogee Hsieh authored
Link status is different from display connected status in the case of something like an Apple dongle where the type-c plug can be connected, and therefore the link is connected, but no sink is connected until an HDMI cable is plugged into the dongle. The sink_count of DPCD of dongle will increase to 1 once an HDMI cable is plugged into the dongle so that display connected status will become true. This checking also apply at pm_resume. Changes in v4: -- none Fixes: 94e58e2d06e3 ("drm/msm/dp: reset dp controller only at boot up and pm_resume") Reported-by:
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- 28 Apr, 2021 1 commit
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Jonathan Marek authored
Increase the minor version to indicate that MSM_PARAM_SUSPENDS is supported. Fixes: 3ab1c5cc ("drm/msm: Add param for userspace to query suspend count") Signed-off-by:
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- 27 Apr, 2021 4 commits
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Dmitry Baryshkov authored
msm_dsi_phy_get_clk_provider() always returns two provided clocks, so return 0 instead of returning incorrect -EINVAL error code. Fixes: 5d134596 ("drm/msm/dsi: push provided clocks handling into a generic code") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Abhinav Kumar <abhinavk@codeaurora.org> Tested-by:
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Dmitry Baryshkov authored
The parent_name initialization was lost in refactoring, restore it now. Fixes: 5d134596 ("drm/msm/dsi: push provided clocks handling into a generic code") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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Jonathan Marek authored
mmu500 targets don't have a "cx_mem" region, set llc_mmio to NULL in that case to avoid the IS_ERR() condition in a6xx_llc_activate(). Fixes: 3d247123 ("drm/msm/a6xx: Add support for using system cache on MMU500 based targets") Signed-off-by:
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Rob Clark authored
Our initial logic for excluding dma-bufs was not quite right. In particular we want msm_gem_get/put_pages() path used for exported dma-bufs to increment/decrement the pin-count. Also, in case the importer is vmap'ing the dma-buf, we need to be sure to update the object's status, because it is now no longer potentially evictable. Fixes: 63f17ef8 drm/msm: Support evicting GEM objects to swap Signed-off-by:
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- 09 Apr, 2021 4 commits
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Kalyan Thota authored
During crtc disable, display perf structures are reset to 0 which includes state varibles which are immutable. On crtc enable, we use the same structures and they don't refelect the actual values 1) Fix is to avoid updating the state structures during disable. 2) Reset the perf structures during atomic check when there is no modeset enable. Signed-off-by:
Kalyan Thota <kalyan_t@codeaurora.org> Reported-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1616158446-19290-1-git-send-email-kalyan_t@codeaurora.orgSigned-off-by:
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AngeloGioacchino Del Regno authored
If pp autorefresh is up (from bootloader splash), we will surely get vblank and pp timeouts. Ensure it is turned off. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Link: https://lore.kernel.org/r/20210406214726.131534-4-marijn.suijten@somainline.orgSigned-off-by:
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Marijn Suijten authored
Neither vtotal nor drm_mode_vrefresh contain a value that is premultiplied by 100 making the x100 variable name incorrect and resulting in vclks_line to become 100 times larger than it is supposed to be. The hardware counts 100 clockticks too many before tearcheck, leading to severe panel issues on at least the Sony Xperia lineup. This is likely an artifact from the original MDSS DSI panel driver where the calculation [1] corrected for a premultiplied reference framerate by 100 [2]. It does not appear that the above values were ever premultiplied in the history of the DRM MDP5 driver. With this change applied the value written to the SYNC_CONFIG_VSYNC register is now identical to downstream kernels. [1]: https://source.codeaurora.org/quic/la/kernel/msm-3.18/tree/drivers/video/msm/mdss/mdss_mdp_intf_cmd.c?h=LA.UM.8.6.c26-02400-89xx.0#n288 [2]: https://source.codeaurora.org/quic/la/kernel/msm-3.18/tree/drivers/video/msm/mdss/mdss_dsi_panel.c?h=LA.UM.8.6.c26-02400-89xx.0#n1648Reviewed-by:
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Marijn Suijten authored
Leaving this at a close-to-maximum register value 0xFFF0 means it takes very long for the MDSS to generate a software vsync interrupt when the hardware TE interrupt doesn't arrive. Configuring this to double the vtotal (like some downstream kernels) leads to a frame to take at most twice before the vsync signal, until hardware TE comes up. In this case the hardware interrupt responsible for providing this signal - "disp-te" gpio - is not hooked up to the mdp5 vsync/pp logic at all. This solves severe panel update issues observed on at least the Xperia Loire and Tone series, until said gpio is properly hooked up to an irq. Suggested-by:
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- 07 Apr, 2021 26 commits
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Krishna Manikandan authored
Some irqs which are applicable for sdm845 target are no longer applicable for sc7180 and sc7280 targets. Add a flag to indicate the irqs which are obsolete for a particular target so that these irqs are skipped while checking for matching irq lookup index. Signed-off-by:
Krishna Manikandan <mkrishn@codeaurora.org> Link: https://lore.kernel.org/r/1617688895-26275-4-git-send-email-mkrishn@codeaurora.orgSigned-off-by:
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Krishna Manikandan authored
INTF_5 is used by EDP panel in SC7280 target. Add vsync and underrun irqs needed by INTF_5 to dpu irq map. Signed-off-by:
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Krishna Manikandan authored
Currently, each register in the dpu interrupt set is allowed to have a maximum of 32 interrupts. With the introduction of INTF_5_VSYNC and INTF_5_UNDERRUN irqs for EDP panel, the total number of interrupts under INTR_STATUS register in dpu_irq_map will exceed 32. Increase the range of each interrupt register to 64 to handle this. This patch has dependency on the below series: https://patchwork.kernel.org/project/linux-arm-msm/list/?series=461193Signed-off-by:
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Krishna Manikandan authored
The reset value of INTF_CONFIG2 register is changed for SC7280 family. Changes are added to program this register correctly based on the target. DATA_HCTL_EN in INTF_CONFIG2 register allows data to be transferred at a different rate than video timing. When this is set, the number of data per line follows DISPLAY_DATA_HCTL register value. This change adds support to program these registers for sc7280 target. Signed-off-by:
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Krishna Manikandan authored
A new register called CTL_FETCH_ACTIVE is introduced in SC7280 family which is used to inform the HW about the pipes which are active in the current ctl path. This change adds support to program this register based on the active pipes in the current composition. Signed-off-by:
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Krishna Manikandan authored
Interface block offsets are different for SC7280 family when compared to existing targets. These offset values are used to access the interface irq registers. This change adds proper interface offsets for SC7280 target. Signed-off-by:
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Krishna Manikandan authored
Add required display hw catalog changes for SC7280 target. Signed-off-by:
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Rob Clark authored
Now that tracking is wired up for potentially evictable GEM objects, wire up shrinker and the remaining GEM bits for unpinning backing pages of inactive objects. Disabled by default for now, with an 'enable_eviction' module param to enable so that we can get some more testing on the range of generations (and iommu pairings) supported. Signed-off-by:
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Rob Clark authored
Shoot down any mmap's *first* before put_pages(). Also add a WARN_ON that the object is locked (to make it clear that this doesn't race with msm_gem_fault()) and remove a redundant WARN_ON (since is_purgable() already covers that case). Fixes: 68209390 ("drm/msm: shrinker support") Signed-off-by:
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Rob Clark authored
Objects that are potential for swapping out are (1) willneed (ie. if they are purgable/MADV_WONTNEED we can just free the pages without them having to land in swap), (2) not on an active list, (3) not dma-buf imported or exported, and (4) not vmap'd. This repurposes the purged list for objects that do not have backing pages (either because they have not been pinned for the first time yet, or in a later patch because they have been unpinned/evicted. Signed-off-by:
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Rob Clark authored
Currently nearly everything, other than newly allocated objects which are not yet backed by pages, is pinned and resident in RAM. But it will be nice to have some stats on what is unpinned once that is supported. Signed-off-by:
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Rob Clark authored
Currently these always go together, either when we purge MADV_WONTNEED objects or when the object is freed. But for unpin, we want to be able to purge (unmap from iommu) the vma, while keeping the iova range allocated (so we can remap back to the same GPU virtual address when the object is re-pinned. Signed-off-by:
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Rob Clark authored
Currently this doesn't matter since we keep the pages pinned until the object is destroyed. But when we start unpinning pages to allow objects to be evicted to swap, it will. Signed-off-by:
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Rob Clark authored
So we don't have to duplicate the boilerplate for eviction. This also lets us re-use the main scan loop for vmap shrinker. Signed-off-by:
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Rob Clark authored
If you mess something up, you don't really need to see the same warn on splat 4000 times pumped out a slow debug UART port.. Signed-off-by:
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Dmitry Baryshkov authored
Currently DPU driver scales bandwidth and core clock for sc7180 only, while the rest of chips get static bandwidth votes. Make all chipsets scale bandwidth and clock per composition requirements like sc7180 does. Drop old voting path completely. Tested on RB3 (SDM845) and RB5 (SM8250). Signed-off-by:
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Dmitry Baryshkov authored
Fill clk_inefficiency_factor, bw_inefficiency_factor and min_prefill_lines in hw catalog data for sdm845 and sm8[12]50. Efficiency factors are blindly copied from sc7180 data, while min_prefill_lines is based on downstream display driver. Signed-off-by:
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Dmitry Baryshkov authored
SM8250 platform has a 8-Levels VIG QoS setting. This setting was missed due to bad interaction with b8dab65b ("drm/msm/dpu: Move DPU_SSPP_QOS_8LVL bit to SDM845 and SC7180 masks"), which was applied in parallel. Fixes: d21fc5df ("drm/msm/dpu1: add support for qseed3lite used on sm8250") Signed-off-by:
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Dmitry Baryshkov authored
Phy driver already knows the source PLL id basing on the set usecase and the current PLL id. Stop passing it to the phy_enable call. As a reminder, dsi manager will always use DSI 0 as a clock master in a slave mode, so PLL 0 is always a clocksource for DSI 0 and it is always a clocksource for DSI 1 too unless DSI 1 is used in the standalone mode. Signed-off-by:
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Dmitry Baryshkov authored
The src_truthtable config is not used for some of phys, which use other means of configuring the master/slave usecases. Inline this function with the goal of removing src_pll_id argument in the next commit. Signed-off-by:
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Dmitry Baryshkov authored
The 7nm, 10nm and 14nm drivers would store interim data used during VCO/PLL rate setting in the global dsi_pll_Nnm structure. Move this data structures to the onstack storage. While we are at it, drop unused/static 'config' data, unused config fields, etc. Signed-off-by:
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Dmitry Baryshkov authored
Drop duplicate fields pdev and id from dsi_pll_Nnm instances. Reuse those fields from the provided msm_dsi_phy. Signed-off-by:
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Dmitry Baryshkov authored
All PHY drivers would map dsi_pll area. Some PHY drivers would also map dsi_phy area again (a leftover from old PHY/PLL separation). Move all ioremaps to the common dsi_phy driver code and drop individual ioremapped areas from PHY drivers. Signed-off-by:
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Dmitry Baryshkov authored
Replace PLL accessor functions (pll_read/pll_write*) with the DSI PHY accessors, reducing duplication. Signed-off-by:
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Dmitry Baryshkov authored
Drop the struct msm_dsi_pll abstraction, by including vco's clk_hw directly into struct msm_dsi_phy. Signed-off-by:
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Dmitry Baryshkov authored
Make save_state/restore callbacks accept struct msm_dsi_phy rather than struct msm_dsi_pll. This moves them to struct msm_dsi_phy_ops, allowing us to drop struct msm_dsi_pll_ops. Signed-off-by:
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