- 16 Mar, 2020 2 commits
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Abel Vesa authored
The device needs to be passed on to the clk_hw_register. Fixes: 1f9aec96 ("clk: imx: clk-gate2: Switch to clk_hw based API") Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Laurent Pinchart authored
The PXP has a single CCGR clock gate, gating both the IPG_CLK_ROOT and the MAIN_AXI_CLK_ROOT. Add a single clock to cover both. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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- 11 Mar, 2020 4 commits
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Anson Huang authored
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Signed-off-by:
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Anson Huang authored
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by:
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Anson Huang authored
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by:
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Anson Huang authored
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by:
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- 10 Mar, 2020 4 commits
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Peng Fan authored
It is not good to use enable/disable for PLLv4 which needs time to lock, because enable/disable is expected to be able run in interrupt context. So use prepare/unprepare. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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Peng Fan authored
pfdv2 is only used in i.MX7ULP. To get best pfd output, the i.MX7ULP Datasheet defines two best PLL rate and pfd frac. Per Datasheel All PLLs on i.MX 7ULP either have VCO base frequency of 480 MHz or 528 MHz. So when determine best rate, we also determine best parent rate which could match the requirement. For some reason the current parent might not be 480MHz or 528MHz, so we still take current parent rate as a choice. And we also enable flag CLK_SET_RATE_PARENT to let parent rate to be configured. Signed-off-by:
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Peng Fan authored
Per clk_ops, compared with round_rate, determine_rate could optionally support the parent clock that should be used to provide the clock rate. In this patch, the parent clock is just parent->rate as round_rate. The following patch will calculate the best parent clock. Signed-off-by:
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Anson Huang authored
Fix below division by zero warning: [ 3.176443] Division by zero in kernel. [ 3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124 [ 3.191817] Hardware name: Freescale i.MX7ULP (Device Tree) [ 3.197821] Workqueue: events dbs_work_handler [ 3.202849] [<c01127d8>] (unwind_backtrace) from [<c010cd80>] (show_stack+0x10/0x14) [ 3.211058] [<c010cd80>] (show_stack) from [<c0c77e68>] (dump_stack+0xd8/0x110) [ 3.218820] [<c0c77e68>] (dump_stack) from [<c0c753c0>] (Ldiv0_64+0x8/0x18) [ 3.226263] [<c0c753c0>] (Ldiv0_64) from [<c05984b4>] (clk_pfdv2_set_rate+0x54/0xac) [ 3.234487] [<c05984b4>] (clk_pfdv2_set_rate) from [<c059192c>] (clk_change_rate+0x1a4/0x698) [ 3.243468] [<c059192c>] (clk_change_rate) from [<c0591a08>] (clk_change_rate+0x280/0x698) [ 3.252180] [<c0591a08>] (clk_change_rate) from [<c0591fc0>] (clk_core_set_rate_nolock+0x1a0/0x278) [ 3.261679] [<c0591fc0>] (clk_core_set_rate_nolock) from [<c05920c8>] (clk_set_rate+0x30/0x64) [ 3.270743] [<c05920c8>] (clk_set_rate) from [<c089cb88>] (imx7ulp_set_target+0x184/0x2a4) [ 3.279501] [<c089cb88>] (imx7ulp_set_target) from [<c0896358>] (__cpufreq_driver_target+0x188/0x514) [ 3.289196] [<c0896358>] (__cpufreq_driver_target) from [<c0899b0c>] (od_dbs_update+0x130/0x15c) [ 3.298438] [<c0899b0c>] (od_dbs_update) from [<c089a5d0>] (dbs_work_handler+0x2c/0x5c) [ 3.306914] [<c089a5d0>] (dbs_work_handler) from [<c0156858>] (process_one_work+0x2ac/0x704) [ 3.315826] [<c0156858>] (process_one_work) from [<c0156cdc>] (worker_thread+0x2c/0x574) [ 3.324404] [<c0156cdc>] (worker_thread) from [<c015cfe8>] (kthread+0x134/0x148) [ 3.332278] [<c015cfe8>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) [ 3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8) [ 3.345314] 5fa0: 00000000 00000000 00000000 00000000 [ 3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 Signed-off-by:
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- 24 Feb, 2020 7 commits
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Anson Huang authored
No need to initialize 'ret' in many functions, as it will get the return value from function call, so remove the initializtion of 'ret'. Signed-off-by:
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Anson Huang authored
When pll type is invalid, ONLY output error message is NOT enough, should return error immediately. Signed-off-by:
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Peng Fan authored
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk Reviewed-by:
Jacky Bai <ping.bai@nxp.com> Signed-off-by:
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Peng Fan authored
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk. Fixes: 96d6392b ("clk: imx: Add support for i.MX8MN clock driver") Reviewed-by:
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Peng Fan authored
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clock Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Reviewed-by:
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Peng Fan authored
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which violates the CCM. There is a CORE_SEL slice before A53 core, we need to configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clock Fixes: db27e40b ("clk: imx8mq: Add the missing ARM clock") Reviewed-by:
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Anson Huang authored
On i.MX8MP, internal HDMI 27M clock is actually 24MHz, so rename the IMX8MP_CLK_HDMI_27M to IMX8MP_CLK_HDMI_24M. Signed-off-by:
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- 19 Feb, 2020 3 commits
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Anson Huang authored
There is nothing in use from init.h/of.h, remove them. Signed-off-by:
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Anson Huang authored
There is nothing in use from init.h/of.h, remove them. Signed-off-by:
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Anson Huang authored
slab.h is necessary and included indirectly by clkdev.h, actually, there is nothing in use from clkdev.h, so just include slab.h instead of clkdev.h. Signed-off-by:
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- 17 Feb, 2020 10 commits
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Anson Huang authored
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by:
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Anson Huang authored
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by:
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Anson Huang authored
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by:
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Anson Huang authored
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by:
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Anson Huang authored
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by:
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Anson Huang authored
The i.MX7ULP clock driver is provider, NOT consumer, so clk-provider.h should be used instead of clk.h. Signed-off-by:
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Anson Huang authored
No need to initialize flags as 0, remove the initialization. Signed-off-by:
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Anson Huang authored
The i.MX8M SoCs clock driver are provider, NOT consumer, so clk-provider.h should be used instead of clk.h. Signed-off-by:
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Fabio Estevam authored
Add CLKO2 support, which is useful for debugging purposes. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
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Fabio Estevam authored
The CLKO1 clock source select list is the following as per the i.MX8MM Reference Manual (put in increasing order): 000 - 24M_REF_CLK 001 - SYSTEM_PLL1_CLK 010 - None 011 - SYSTEM_PLL1_DIV4 100 - AUDIO_PLL2_CLK 101 - SYSTEM_PLL2_DIV2 110 - VPU_PLL_CLK 111 - SYSTEM_PLL1_DIV10 Fix it accordingly. Fixes: ba5625c3 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by:
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- 14 Feb, 2020 5 commits
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Peng Fan authored
Use imx8m_clk_hw_composite_core to simplify code. Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility Reviewed-by:
Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by:
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Peng Fan authored
Use imx8m_clk_hw_composite_core to simplify code. Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility Reviewed-by:
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Peng Fan authored
Use imx8m_clk_hw_composite_core to simplify code. Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility Reviewed-by:
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Peng Fan authored
There are several clock slices, current composite code only support bus/ip clock slices, it could not support core slice. So introduce a new API imx8m_clk_hw_composite_core to support core slice. To core slice, post divider with 3 bits width and no pre divider. Other fields are same as bus/ip slices. Add a flag IMX_COMPOSITE_CORE for the usecase. Reviewed-by:
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Peng Fan authored
Add ocotp root clk, then when using nvmem to read fuse, clk could be managed. Signed-off-by:
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- 13 Feb, 2020 5 commits
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Anson Huang authored
Add new frequency entries to pll1443x table to meet different display settings requirement. Signed-off-by:
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Anson Huang authored
Refine i.MX8MN clock binding by removing useless content and updating the example, it makes all i.MX8M SoCs' clock binding aligned. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Anson Huang authored
Convert the i.MX8MM clock binding to DT schema format using json-schema Signed-off-by:
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Anson Huang authored
Convert the i.MX8MQ clock binding to DT schema format using json-schema Signed-off-by:
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Horia Geantă authored
i.mx8mn has support for clock gating the snvs module. Add it into clock tree so that rtc-snvs driver could use it. Note this will also be required in the snvs_pwrkey driver, once support for clock management will be added. Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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