- 22 Jun, 2019 40 commits
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Nikola Cornij authored
[why] With DSC power gating enabled, one of the register reads times out occasionally, causing a DSC test to fail. [how] Disable DSC power gating in Diags. NOTE: This has to be reverted once the problems with DSC power gating are resolved. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Joshua Aberback authored
[Why] We want a test pattern to show up on screen when we're blanked and have visual confirm enabled, for debugging. Raven does this, it's a mistake that Navi does not. [How] - in "blank_pixel_data", set appropriate DPG pattern for visual confirm - refactor DPG calls out of "enable_stream_timing" Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Dmytro Laktyushkin authored
* add plane state null checks * add and set update surface flags Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Tyler DiBattista authored
[Why] these enums/structs will be used more generically in the future so moving it to dc_hw_types and dc_types Signed-off-by:
Tyler DiBattista <tyler.dibattista@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Vitaly Prosyak authored
[Why & How] Reuse existent code path (dcn1+) and in order to do that apply de gamma in 1D blender LUT and re use MPC OGAM. Follow up is required. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Charlene Liu authored
[Description] Features that are desirable for minimizing the Global Sync Period: DRR and lateflip Signed-off-by:
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Wenjing Liu authored
Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] In compute dsc bandwidth range there is an uninitialized variable [how] Initialize the variable to the correct value. Signed-off-by:
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Leo (Hanghong) Ma authored
[Why] To send sdp message immediately from a single slot. [How] Modify the generic SDP message interface, and use GSP4 to send immediate sdp message. Signed-off-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Ilya Bakoulin authored
DCN2.0 LB BPP should be 48 or 16BPC and max cursor width should be 256. Also use populate_dml_pipes as functions pointer instead of using it directly Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
A regression was introduced when we set correct tile size for the gfx9 swizzle mode. This resulted in incorrect macro tile size. Signed-off-by:
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Joshua Aberback authored
[Why] Plane disable gets calls when we enable blank. On DCN2, we blank by using DPG to display a black colour instead of using OTG blank. DPG runs off the OPP clock, therefore we shouldn't disable the OPP clock when disabling the plane. We do need to disable the OPP clock when disabling the entire pipe, that will be addressed in a separate commit. Signed-off-by:
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Dmytro Laktyushkin authored
It looks like mpo isn't properly disabled during odm, this change is meant to fix that. Signed-off-by:
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Charlene Liu authored
dwb fixes. Signed-off-by:
Duke Du <Duke.Du@amd.com> Acked-by:
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Charlene Liu authored
[Description] dcn20 has num_dwb =1 in the res cap, but not created. Signed-off-by:
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Aric Cyr authored
[Why] GSL is being used to synchronize pipes when vsync is off but on transition to vsync on during a mode change GSL is not being reset correctly. [How] Disable GSL on any plane that is disabled. Signed-off-by:
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Nikola Cornij authored
[why] A few of the new DSC DPCD caps were introduced by a DP 1.4a SCR in order to give DSC branch decoders a chance to expose their maximum throughput and maximum line width limitations. Signed-off-by:
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Nikola Cornij authored
[why] If a set is done, DSC settings are zeroed out, leading to no DSC for the modes that require ODM, such as 8k60. This was a regression introduced by 5a4f26295176bbfc776c75aaf0f6dd8ccf806958. Signed-off-by:
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Vitaly Prosyak authored
[Why & How] Gamut map lib provides a wider gamut mapping options vs BT2390 Signed-off-by:
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Samson Tam authored
[Why] Emulating passive dongle on USB-C port causes issue on some asics. [How] Check for DP_IS_USB_C flag in bios parser and propagate it to encoder features flags. If DP_IS_USB_C flag is set and it is trying to emulate passive dongle, then return fail. Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric. If the memory controller is fully utilized and the DCHub requestors are well ahead of their amortized schedule, then it is safe to prevent the next winner from being committed and sent to the fabric. The utilization of the memory controller is approximated by ensuring that the number of outstanding requests is greater than a threshold specified by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule, the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles. [How] The recommended settings to enable thise dynamic limiting for Navi is 180 requests. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Nikola Cornij authored
[why] It was missing, although defined in DP spec [how] - Add handling of this value to DSC code - Also remove unused file dsc_helpers.c Signed-off-by:
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Charlene Liu authored
[Description] This is for DC_I2c arbitration use between HW use/SW use and DMCU use. Signed-off-by:
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Nikola Cornij authored
[why] 'Divide by zero' error happens when line size happens to be zero. [how] The code that makes sure line size minimum value can be 1 was already present in DCN1 part of the driver, this is mearly a port to DCN2. Signed-off-by:
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Eryk Brol authored
[Why] In order to ensure that incoming flips are latched and complete immediately, we need to program the vupdate interrupt to come during the back porch of each frame. [How] Program the vupdate start_line to be in the back porch like it's done for DCN1. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
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Yongqiang Sun authored
Refactor programming watermark function: Divided into urgent watermark, stutter watermark and pstate watermark. Signed-off-by:
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Dmytro Laktyushkin authored
The split condition is broken and will always activate at the moment. Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Charlene Liu authored
Different HW will need to init HUBP differently. For now, add a vtable entry, and hook a NO-OP for DCN1 and DCN2. In addition, future HW will need to access the HUBPREQ_DEBUG and CUR_TTU_CNTL0 register for hubp_init. Add that here. Signed-off-by:
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Ilya Bakoulin authored
[Why] OPTC data format was left at its default value (444) when enabling ODM combine. This caused issues with FPGA capture. [How] Write the OPTC_DATA_FORMAT field when enabling ODM combine. Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
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Thomas Lim authored
[Why] Due to the generic introduction of seamless boot, the display is no longer blanked upon boot. However, this causes corruption on some systems that does not lock the memory in the non-secure boot case, resulting in brief corruption on boot due to garbage being written into the frame buffer. [How] Add a flag, read during DC init, to determine whether display should be blanked on boot. Default to true. Signed-off-by:
Thomas Lim <Thomas.Lim@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Nikola Cornij authored
[why] DSC target bpp precision is a decoder DPCD and an AMD encoder capability. It must be taken into account when calculating target bitrate. [how] Add a DC DSC function that does this calculation. Signed-off-by:
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Josip Pavic authored
[Why] ABM is currently not enabled on DCN2. [How] Update the register name list for DCN2 and un-comment the code that creates the abm object. Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] The current policy will always enable DSC to 12 bpp regardless of if the current bandwidth is enough for MST displays. This logic is not optimal because user will get lower quality output if DSC compression is enabled. This change to is to implement a DSC MST bandwidth fair share algorithm so we will dynamically decide if DSC is needed and what quality (target bpp) is needed to fairly destribute the MST bandwidth in one MST topology. This will allow user to see the most optimal image quality with the given bandwidth. [how] We will start with lowest bandwidth possible and run a Max-Min fairness algorithm to fairly distribute the available bandwidth. If there is still remaining bandwidth, we will try to fit the timing without DSC compression. Signed-off-by:
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Nikola Cornij authored
[why] There are ASICs that have fewer DSC engines than pipes, which makes DSC a resource that should be used only if required. [how] Acquire DSC HW resource if required by stream and release when not required anymore. Signed-off-by:
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hersen wu authored
[WHY] system crash when initialize dwb current linux driver does not support dwb. disable this feature for now. [HOW] set num_dwb = 0 to disable dwb for now Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
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hersen wu authored
[WHY] linux upstream already has interrupt vupdate for freesync in dcn10. dcn20 interrupt shares the same source code as dcn10. but dcn20 interrupt translator does not add vupdate interrupt. this cause index of vupdate aarray be negative which causes crash. [HOW] add vupdate into dc interrupt transltor Signed-off-by:
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Nikola Cornij authored
[why] DSC resource has to be acquired before it can be used and simply copying a reference to it is very likely to cause problems when accessing DSC. [how] Set DSC resource pointer to NULL to mark it as unused after primary pipe resources were copied to the secondary ODM pipe. Signed-off-by:
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Tyler DiBattista authored
[Why] Some nightly tests are failing since the new value for fclk is a bit too low. Also, a new test for the maximum downscale case was needed. [How] Updated the default value for fclk to be 1.2GHz. Signed-off-by:
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Wenjing Liu authored
[why] when an update programming sequence requires both front end and back end pipe to be updated synchronously, a global update lock needs to be set to ensure that we don't get a frame with only front end update but not the back end update. [how] setup global lock parameters on enable_stream_timing. enable global lock when pipe_control_lock_global is called. disable global lock when pipe_control_lock is called. Signed-off-by:
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