- 05 May, 2016 40 commits
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Christian König authored
Not needed any more. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Christian König authored
This allows us to have small BOs on the LRU before big ones. v2: fix of by one and list corruption bug Signed-off-by:
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Dave Airlie authored
This isn't being used so drop it. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
we introduced vmid fence, so one hw submission could produce two fences. Signed-off-by:
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Alex Deucher authored
Acked-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
They care common for all sdma 3.0 parts Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
They can be used for other VI parts. Acked-by:
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Alex Deucher authored
v2: just enable MGCG for now since CGCG causes hangs Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
They can be shared with other asics with minor modifications. Acked-by:
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Alex Deucher authored
Different asics tend to have different ways to interact with the RLC. This just covers enter/exit of safe mode for updating CG and PG state, but could be extended to cover other RLC operations in the future if necessary. Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
So it can be shared with CZ/ST. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
We were already enabling these CG features, this uses the standard interface for doing so. Acked-by:
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Alex Deucher authored
Acked-by:
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Christian König authored
This allows fine grained control for the driver where to add a BO into the LRU. v2: fix typo in comment Reviewed-by:
Sinclair Yeh <syeh@vmware.com> Signed-off-by:
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Christian König authored
Useful for driver specific LRU handling. v2: fix typo in comment Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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Christian König authored
Not used any more. Reviewed-by:
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Christian König authored
When we use an extern reservation object that otherwise waits for every fence registered with it. Reviewed-by:
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Christian König authored
No functional change. Signed-off-by:
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Christian König authored
Instead of hard coding just another name in the ring code. v2: squash in Tom's rebase fix Signed-off-by:
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Christian König authored
Those are way too large. Signed-off-by:
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Christian König authored
Those are way too large. Signed-off-by:
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Christian König authored
Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions. This fixes UVD with 8 concurrent submissions or more. Signed-off-by:
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Eric Huang authored
Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
Signed-off-by:
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Felix Kuehling authored
TTM BO accounting is out of sync with how memory is really allocated in ttm[_dma]_tt_alloc_page_directory. This resulted in excessive estimated overhead with many small allocations. ttm_dma_tt_alloc_page_directory makes a single allocation for three arrays: pages, DMA and CPU addresses. It uses drm_calloc_large, which uses kmalloc internally for allocations smaller than PAGE_SIZE. ttm_round_pot should be a good approximation of its memory usage both above and below PAGE_SIZE. Reviewed-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Reviewed-by:
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Dave Airlie authored
This is just a type-safety things to avoid everyone taking void *, it doesn't change anything. v2: agd5f: split out the dal changes into a separate patch. Signed-off-by:
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Arindam Nath authored
Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by:
Arindam Nath <arindam.nath@amd.com> Signed-off-by:
Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by:
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Nils Wallménius authored
These tables were initialized on stack on each call, avoid that and save a little bit of text size. Reviewed-by:
Nils Wallménius <nils.wallmenius@gmail.com> Signed-off-by:
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