- 04 Mar, 2014 6 commits
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Jason Cooper authored
With kirkwood migrating into mach-mvebu, mvebu_v5_defconfig needs to select ARCH_MVEBU. Unfortunately, this means that when building a v5 kernel, we unnecessarily build dtbs for the armada v7 boards. To fix this, we instead select based on MACH_ARMADA_* on a per SoC basis. Reported-by:
Kevin Hilman <khilman@linaro.org> Acked-by:
Jason Cooper <jason@lakedaemon.net>
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Jason Cooper authored
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Sebastian Hesselbarth authored
We share global config registers by syscon node, add it to dove.dtsi. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
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Sebastian Hesselbarth authored
Dove pinctrl uses additional registers to control MPPs. This patch first increases existing pinctrl reg property by one register, and then adds two new ranges for MPP4 and PMU MPP registers. Signed-off-by:
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Andrew Lunn authored
Make use of the mvebu system controller, by placing a node into the dtsi file. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Acked-by:
Arnd Bergmann <arnd@arndb.de> Tested-by:
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by:
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Andrew Lunn authored
Now that the Feroceon L2 cache has a DT binding, make use of it. Signed-off-by:
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- 22 Feb, 2014 7 commits
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Jason Cooper authored
mvebu dt fixes for v3.14 - mvebu: add missing 'eth3' alias for mv78260 - dove: revert PMU interrupt controller node, wait for driver to land.
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Thomas Petazzoni authored
Instead of hardcoding the values of the interrupt flags, use the macros provided by <include/dt-bindings/interrupt-controller/irq.h> and <include/dt-bindings/interrupt-controller/arm-gic.h> for the Armada 375 and Armada 38x Device Tree files. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Thomas Petazzoni authored
Instead of hardcoding 0 and 1 to indicate SPI and PPI GIC interrupts, use the definitions of <dt-bindings/interrupt-controller/arm-gic.h> to clarify the Device Tree code. Signed-off-by:
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Thomas Petazzoni authored
Some of the Armada 375/38x DTs that were recently submitted were still using the old-style /include/ instead of the new-style, C-preprocessor based #include. Since we are going to start including more headers, switching to the C-preprocessor based includes is important. Signed-off-by:
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Ben Peddell authored
Add device tree fragments and files to support many of the kirkwood based Synology NAS devices. This is a modification of Andrew Lunn's <andrew@lunn.ch> translation of the board setup file maintained by Ben Peddell <klightspeed@killerwolves.net> The Ricoh RS5C372 RTC was used in all 2009 units and some 2010 units. All other Synology Kirkwood-based DiskStations and RackStations use the Seiko S35390A RTC. Most of the 1-bay and 2-bay units use the GPIOs that are multiplexed with the built-in SATA interface activity/presence pins on mpp 20-23, while the 4-bay units use ge01 and a PCIe SATA controller, and put the software controlled HDD leds on mpp 36-43. Most of the 6281 units with HDD power controls use mpp 29 and 31, while most of the 6282 units with HDD power controls use mpp 30, 34, 44 and 45 and provide a model ID on mpp 28, 29, 46 and 47. Pre-2012 units and most 4-bay units didn't have a separate power control for HDD1. These power controls are presumably to limit startup current from the 12V brick power supply. Instead of using separate dtsi files in a synology directory, this patch uses a single dtsi file containing all of the modules for these boards, with all of the modules not common to all boards disabled. The board dts files then enable the appropriate modules for their boards. Signed-off-by:
Ben Peddell <klightspeed@killerwolves.net> Tested-by: Ben Peddell <klightspeed@killerwolves.net> (ds211j) Signed-off-by:
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Andrew Lunn authored
Add the Seiko Instruments Inc S35390a to the list of trivial i2c devices. Signed-off-by:
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Andrew Lunn authored
The following patches make use of vendor names: * ricoh (Ricoh Co. Ltd.); * qnap (QNAP Systems, Inc.); * sii (Seiko Instruments, Inc.); and * synology (Synology, Inc.) Add them to the vendor prefix list. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 18 Feb, 2014 1 commit
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Jason Cooper authored
The corresponding driver didn't make it into v3.14, so we need to remove the node. Dove systems fail to boot with the node present and no driver. This node will be re-added when the driver makes it to mainline. Reported-by:
Jean-Francois Moine <moinejf@free.fr> Tested-by:
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- 17 Feb, 2014 13 commits
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Thomas Petazzoni authored
The Armada 385 DB board is the development board from Marvell for the Armada 385 SoC. This commit adds a Device Tree description for this board, which enables the following features: * Network interfaces * I2C buses * SDIO * Serial port * SPI bus, with a SPI flash * PCIe interfaces Signed-off-by:
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Thomas Petazzoni authored
The Armada 380 and 385 SoCs are new SoCs from Marvell, based on a Cortex-A9 cores (single core for 380, dual core for 385) and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPU * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * Pinctrl * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers * Network interfaces Signed-off-by:
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Thomas Petazzoni authored
The Armada 375 DB board is the development board from Marvell for the Armada 375 SoC. This commit adds a Device Tree description for this board, which enables the following features: * I2C buses * SDIO * Serial port * SPI bus, with a SPI flash. Note that the SPI bus is disabled by default, because it conflicts with the NAND, and can only work if the board boots out of SPI. Since most boards are shipped to boot out of NAND, we're default to having the SPI bus disabled. * PCIe interfaces Signed-off-by:
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Gregory CLEMENT authored
The Armada 375 SoC is a new SoC from Marvell, based on a dual core Cortex-A9 and a number of hardware blocks that are common with earlier SoCs from the mvebu family. The provided Device Tree describes the following parts of the SoC: * CPUs * Device Bus * Clocks * Interrupt controllers: GIC and MPIC * GPIO controllers * I2C buses * L2 cache * MBus controller * SDIO * Pinctrl * SATA * Serial * SPI buses * System controller (for reboot) * Timer * XOR engines * PCIe controllers Signed-off-by:
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Ezequiel Garcia authored
Add the devicetree node to enable watchdog support available in Dove SoCs. Tested-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by:
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Ezequiel Garcia authored
In order to support multiplatform builds the watchdog devicetree binding was modified and now the 'reg' property is specified to need two entries. This commit adds the second entry as-per the new specification. Tested-by:
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Ezequiel Garcia authored
Add the DT nodes to enable watchdog support available in Armada 370 and Armada XP SoCs. Tested-by:
Willy Tarreau <w@1wt.eu> Signed-off-by:
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Andrew Lunn authored
Perform a mechanical translation of rd88f6281-setup.c into DT. Since the hardware differs between the A0 and A1 stepping, two dts files are used, and a .dtsi file for the common parts. The A0 part does not have a "wan" port on the switch and uses PHY address 10 to address the switch. The A1 part does have the "wan" port and uses address 0. Signed-off-by:
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Andrew Lunn authored
Mechanically translate rd88f6192-nas-setup.c into DT equivelent. Signed-off-by:
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Thomas Petazzoni authored
In addition to the analog audio input and output, the Armada 370 DB also has S/PDIF input and output optical connectors. This commit improves the Device Tree description of the Armada 370 DB platform to enable the S/PDIF support. Signed-off-by:
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Thomas Petazzoni authored
This commit adds the necessary Device Tree informations to enable audio support on the Armada 370 DB platform. In details it: * Instantiates the CS42L51 audio codec on the I2C0 bus, and configures this bus with the appropriate pin-muxing configuration. * Enables the I2S audio controller, and configures it with the appropriate pin-muxing configuration. * Through hog pins, ensures that the other pins possibly used for I2S are muxed with another function than I2S. Signed-off-by:
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Thomas Petazzoni authored
This commit adds a pin-muxing configuration for the I2C0 bus of the Armada 370, which is used on the Armada 370 DB platform to interface with the CS42L51 audio codec. Signed-off-by:
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Thomas Petazzoni authored
The Armada 370 SoC has an I2S audio controller. This commit adds the description of this controller to the Device Tree describing this SoC, as well as two possible muxing configurations for the I2S bus pins. Signed-off-by:
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- 11 Feb, 2014 2 commits
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Thomas Petazzoni authored
Instead of harcoding keycodes specifications in the Armada 370/XP boards, use the <dt-bindings/input/input.h> header file and its keycode definitions. Signed-off-by:
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Thomas Petazzoni authored
Instead of harcoding 0 and 1 for the gpio specifications in the Armada 370/XP boards, use the <dt-bindings/gpio/gpio.h> header file and its GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW definitions. Signed-off-by:
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- 05 Feb, 2014 3 commits
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Willy Tarreau authored
It was correctly set on mv78460 but not on mv78260, resulting in my OpenBlocks AX3-4 retrieving only 3 of its 4 MAC addresses from the boot loader. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Andrew Lunn authored
Re-implement the Marvell Kirkwood ts41x-setup.c in DT. As with the QNAP 119, there are two variants, depending on which SoC has been used. They differ on Ethernet PHY addresses and number of PCIe busses. Signed-off-by:
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Andrew Lunn authored
The Excito Bubba B3 is a home server, single drive NAS box, Wifi access point, etc. Signed-off-by:
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- 03 Feb, 2014 4 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linuxLinus Torvalds authored
Pull parisc updates from Helge Deller: "The three major changes in this patchset is a implementation for flexible userspace memory maps, cache-flushing fixes (again), and a long-discussed ABI change to make EWOULDBLOCK the same value as EAGAIN. parisc has been the only platform where we had EWOULDBLOCK != EAGAIN to keep HP-UX compatibility. Since we will probably never implement full HP-UX support, we prefer to drop this compatibility to make it easier for us with Linux userspace programs which mostly never checked for both values. We don't expect major fall-outs because of this change, and if we face some, we will simply rebuild the necessary applications in the debian archives" * 'parisc-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: add flexible mmap memory layout support parisc: Make EWOULDBLOCK be equal to EAGAIN on parisc parisc: convert uapi/asm/stat.h to use native types only parisc: wire up sched_setattr and sched_getattr parisc: fix cache-flushing parisc/sti_console: prefer Linux fonts over built-in ROM fonts
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Mikulas Patocka authored
HPFS needs to load 4 consecutive 512-byte sectors when accessing the directory nodes or bitmaps. We can't switch to 2048-byte block size because files are allocated in the units of 512-byte sectors. Previously, the driver would allocate a 2048-byte area using kmalloc, copy the data from four buffers to this area and eventually copy them back if they were modified. In the current implementation of the buffer cache, buffers are allocated in the pagecache. That means that 4 consecutive 512-byte buffers are stored in consecutive areas in the kernel address space. So, we don't need to allocate extra memory and copy the content of the buffers there. This patch optimizes the code to avoid copying the buffers. It checks if the four buffers are stored in contiguous memory - if they are not, it falls back to allocating a 2048-byte area and copying data there. Signed-off-by:
Mikulas Patocka <mikulas@artax.karlin.mff.cuni.cz> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Mikulas Patocka authored
Previously, hpfs scanned all bitmaps each time the user asked for free space using statfs. This patch changes it so that hpfs scans the bitmaps only once, remembes the free space and on next invocation of statfs it returns the value instantly. New versions of wine are hammering on the statfs syscall very heavily, making some games unplayable when they're stored on hpfs, with load times in minutes. This should be backported to the stable kernels because it fixes user-visible problem (excessive level load times in wine). Signed-off-by:
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- 02 Feb, 2014 4 commits
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Helge Deller authored
Add support for the flexible mmap memory layout (as described in http://lwn.net/Articles/91829). This is especially very interesting on parisc since we currently only support 32bit userspace (even with a 64bit Linux kernel). Signed-off-by:
Helge Deller <deller@gmx.de>
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Guy Martin authored
On Linux, only parisc uses a different value for EWOULDBLOCK which causes a lot of troubles for applications not checking for both values. Since the hpux compat is long dead, make EWOULDBLOCK behave the same as all other architectures. Signed-off-by:
Guy Martin <gmsoft@tuxicoman.be> Signed-off-by:
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Helge Deller authored
The stat.h header file is exported to userspace. Some userspace applications failed to compile due to missing/unknown types, so we better convert it to use native types only (like it's done on other architectures too). Signed-off-by: -
Helge Deller authored
Signed-off-by:
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