- 26 Jul, 2022 28 commits
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Jakub Kicinski authored
To allow for the logic to change later wrap accesses which interrogate the input skb in helper functions. Signed-off-by:Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski authored
Jiri Pirko says: ==================== Implement dev info and dev flash for line cards This patchset implements two features: 1) "devlink dev info" is exposed for line card (patches 6-9) 2) "devlink dev flash" is implemented for line card gearbox flashing (patch 10) For every line card, "a nested" auxiliary device is created which allows to bind the features mentioned above (patch 4). The relationship between line card and its auxiliary dev devlink is carried over extra line card netlink attribute (patches 3 and 5). The first patch removes devlink_mutex from devlink_register/unregister() which eliminates possible deadlock during devlink reload command. The second patchset follows up with putting net pointer check into new helper. Examples: $ devlink lc show pci/0000:01:00.0 lc 1 pci/0000:01:00.0: lc 1 state active type 16x100G nested_devlink auxiliary/mlxsw_core.lc.0 supported_types: 16x100G $ devlink dev show auxiliary/mlxsw_core.lc.0 auxiliary/mlxsw_core.lc.0 $ devlink dev info auxiliary/mlxsw_core.lc.0 auxiliary/mlxsw_core.lc.0: versions: fixed: hw.revision 0 fw.psid MT_0000000749 running: ini.version 4 fw 19.2010.1312 $ devlink dev flash auxiliary/mlxsw_core.lc.0 file mellanox/fw-AGB-rel-19_2010_1312-022-EVB.mfa2 ==================== Link: https://lore.kernel.org/r/20220725082925.366455-1-jiri@resnulli.usSigned-off-by: -
Jiri Pirko authored
Once line card is activated, check the FW version and PSID are exposed. Signed-off-by:
Jiri Pirko <jiri@nvidia.com> Signed-off-by:
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Jiri Pirko authored
Once line card is provisioned, check if HW revision and INI version are exposed on associated nested auxiliary device. Signed-off-by:
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Jiri Pirko authored
Implement flash_update() devlink op for the line card devlink instance to allow user to update line card gearbox FW using MDDT register and mlxfw. Example: $ devlink dev flash auxiliary/mlxsw_core.lc.0 file mellanox/fw-AGB-rel-19_2010_1312-022-EVB.mfa2 Signed-off-by:
Ido Schimmel <idosch@nvidia.com> Signed-off-by:
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Jiri Pirko authored
Use tunneled MGIR to obtain PSID of line card device and extend device_info_get() op to fill up the info with that. Example: $ devlink dev info auxiliary/mlxsw_core.lc.0 auxiliary/mlxsw_core.lc.0: versions: fixed: hw.revision 0 fw.psid MT_0000000749 running: ini.version 4 fw 19.2010.1312 Signed-off-by: -
Jiri Pirko authored
The MDDT register allows to deliver query and request messages (PRM registers, commands) to a DownStream device. Signed-off-by:
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Jiri Pirko authored
In case the line card is active, go over all possible existing devices (gearboxes) on it and expose FW version of the flashable one. Example: $ devlink dev info auxiliary/mlxsw_core.lc.0 auxiliary/mlxsw_core.lc.0: versions: fixed: hw.revision 0 running: ini.version 4 fw 19.2010.1312 Signed-off-by: -
Jiri Pirko authored
Extend existing MDDQ register by possibility to query information about devices residing on a line card. Signed-off-by:
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Jiri Pirko authored
Implement info_get() to expose HW revision of a linecard and loaded INI version. Example: $ devlink dev info auxiliary/mlxsw_core.lc.0 auxiliary/mlxsw_core.lc.0: versions: fixed: hw.revision 0 running: ini.version 4 Signed-off-by: -
Jiri Pirko authored
In order to be eventually able to expose line card gearbox version and possibility to flash FW, model the line card as a separate device on auxiliary bus. Add the auxiliary device for provisioned line card in order to be able to expose provisioned line card info over devlink dev info. When the line card becomes active, there may be other additional info added to the output. Signed-off-by:
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Jiri Pirko authored
For the purpose of exposing device info and allow flash update which is going to be implemented in follow-up patches, introduce a possibility for a line card to expose relation to nested devlink entity. The nested devlink entity represents the line card. Example: $ devlink lc show pci/0000:01:00.0 lc 1 pci/0000:01:00.0: lc 1 state active type 16x100G nested_devlink auxiliary/mlxsw_core.lc.0 supported_types: 16x100G $ devlink dev show auxiliary/mlxsw_core.lc.0 auxiliary/mlxsw_core.lc.0 Signed-off-by: -
Jiri Pirko authored
Benefit from having devlinks iterator helper devlinks_xa_for_each_registered_get() and move the net pointer check inside. Suggested-by:
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Jiri Pirko authored
Remove dependency on devlink_mutex during devlinks xarray iteration. The reason is that devlink_register/unregister() functions taking devlink_mutex would deadlock during devlink reload operation of devlink instance which registers/unregisters nested devlink instances. The devlinks xarray consistency is ensured internally by xarray. There is a reference taken when working with devlink using devlink_try_get(). But there is no guarantee that devlink pointer picked during xarray iteration is not freed before devlink_try_get() is called. Make sure that devlink_try_get() works with valid pointer. Achieve it by: 1) Splitting devlink_put() so the completion is sent only after grace period. Completion unblocks the devlink_unregister() routine, which is followed-up by devlink_free() 2) During devlinks xa_array iteration, get devlink pointer from xa_array holding RCU read lock and taking reference using devlink_try_get() before unlock. Signed-off-by:
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Paolo Abeni authored
Subbaraya Sundeep says: ==================== Octeontx2 minor tc fixes This patch set fixes two problems found in tc code wrt to ratelimiting and when installing UDP/TCP filters. Patch 1: CN10K has different register format compared to CN9xx hence fixes that. Patch 2: Check flow mask also before installing a src/dst port filter, otherwise installing for one port installs for other one too. ==================== Link: https://lore.kernel.org/r/1658650874-16459-1-git-send-email-sbhatta@marvell.comSigned-off-by:
Paolo Abeni <pabeni@redhat.com>
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Subbaraya Sundeep authored
Check the mask for non-zero value before installing tc filters for L4 source and destination ports. Otherwise installing a filter for source port installs destination port too and vice-versa. Fixes: 1d4d9e42 ("octeontx2-pf: Add tc flower hardware offload on ingress traffic") Signed-off-by:
Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by:
Sunil Goutham <sgoutham@marvell.com> Signed-off-by:
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Sunil Goutham authored
NIX_AF_TLXX_PIR/CIR register format has changed from OcteonTx2 to CN10K. CN10K supports larger burst size. Fix burst exponent and burst mantissa configuration for CN10K. Also fixed 'maxrate' from u32 to u64 since 'police.rate_bytes_ps' passed by stack is also u64. Fixes: e638a83f ("octeontx2-pf: TC_MATCHALL egress ratelimiting offload") Signed-off-by:
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wangjianli authored
Delete the redundant word 'in'. Signed-off-by:
wangjianli <wangjianli@cdjrlc.com> Link: https://lore.kernel.org/r/20220724075207.21080-1-wangjianli@cdjrlc.comSigned-off-by:
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wangjianli authored
Delete the redundant word 'in'. Signed-off-by:
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Jakub Kicinski authored
Christian Marangi says: ==================== Add MTU change with stmmac interface running This series is to permit MTU change while the interface is running. Major rework are needed to permit to allocate a new dma conf based on the new MTU before applying it. This is to make sure there is enough space to allocate all the DMA queue before releasing the stmmac driver. This was tested with a simple way to stress the network while the interface is running. 2 ssh connection to the device: - One generating simple traffic with while true; do free; done - The other making the mtu change with a delay of 1 second The connection is correctly stopped and recovered after the MTU is changed. The first 2 patch of this series are minor fixup that fix problems presented while testing this. One fix a problem when we renable a queue while we are generating a new dma conf. The other is a corner case that was notice while stressing the driver and turning down the interface while there was some traffic. (this is a follow-up of a simpler patch that wanted to add the same feature. It was suggested to first try to check if it was possible to apply the new configuration. Posting as RFC as it does major rework for the new concept of DMA conf) ==================== Link: https://lore.kernel.org/r/20220723142933.16030-1-ansuelsmth@gmail.comSigned-off-by:
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Christian Marangi authored
Remove the limitation where the interface needs to be down to change MTU by releasing and opening the stmmac driver to set the new MTU. Also call the set_filter function to correctly init the port. This permits to remove the EBUSY error while the ethernet port is running permitting a correct MTU change if for example a DSA request a MTU change for a switch CPU port. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
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Christian Marangi authored
Rework the driver to generate the stmmac dma_conf before stmmac_open. This permits a function to first check if it's possible to allocate a new dma_config and then pass it directly to __stmmac_open and "open" the interface with the new configuration. Signed-off-by:
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Christian Marangi authored
Move dma buf conf to dedicated struct. This in preparation for code rework that will permit to allocate separate dma_conf without affecting the priv struct. Signed-off-by:
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Christian Marangi authored
Disable all queues and disconnect before tx_disable in stmmac_release to prevent a corner case where packet may be still queued at the same time tx_disable is called resulting in kernel panic if some packet still has to be processed. Signed-off-by:
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Christian Marangi authored
Move queue reset to dedicated functions. This aside from a simple cleanup is also required to allocate a dma conf without resetting the tx queue while the device is temporarily detached as now the reset is not part of the dma init function and can be done later in the code flow. Signed-off-by:
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William Dean authored
delete extra space and tab in blank line, there is no functional change. Reported-by:
Hacash Robot <hacashRobot@santino.com> Signed-off-by:
William Dean <williamsukatube@gmail.com> Link: https://lore.kernel.org/r/20220723073222.2961602-1-williamsukatube@163.comSigned-off-by:
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Jakub Kicinski authored
Merge tag 'wireless-next-2022-07-25' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next Kalle Valo says: ==================== wireless-next patches for v5.20 Third set of patches for v5.20. MLO work continues and we have a lot of stack changes due to that, including driver API changes. Not much driver patches except on mt76. Major changes: cfg80211/mac80211 - more prepartion for Wi-Fi 7 Multi-Link Operation (MLO) support, works with one link now - align with IEEE Draft P802.11be_D2.0 - hardware timestamps for receive and transmit mt76 - preparation for new chipset support - ACPI SAR support * tag 'wireless-next-2022-07-25' of git://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next: (254 commits) wifi: mac80211: fix link data leak wifi: mac80211: mlme: fix disassoc with MLO wifi: mac80211: add macros to loop over active links wifi: mac80211: remove erroneous sband/link validation wifi: mac80211: mlme: transmit assoc frame with address translation wifi: mac80211: verify link addresses are different wifi: mac80211: rx: track link in RX data wifi: mac80211: optionally implement MLO multicast TX wifi: mac80211: expand ieee80211_mgmt_tx() for MLO wifi: nl80211: add MLO link ID to the NL80211_CMD_FRAME TX API wifi: mac80211: report link ID to cfg80211 on mgmt RX wifi: cfg80211: report link ID in NL80211_CMD_FRAME wifi: mac80211: add hardware timestamps for RX and TX wifi: cfg80211: add hardware timestamps to frame RX info wifi: cfg80211/nl80211: move rx management data into a struct wifi: cfg80211: add a function for reporting TX status with hardware timestamps wifi: nl80211: add RX and TX timestamp attributes wifi: ieee80211: add helper functions for detecting TM/FTM frames wifi: mac80211_hwsim: handle links for wmediumd/virtio wifi: mac80211: sta_info: fix link_sta insertion ... ==================== Link: https://lore.kernel.org/r/20220725174547.EA465C341C6@smtp.kernel.orgSigned-off-by:
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Alexander Stein authored
These properties are inherited from ethernet-controller.yaml. This fixes the dt_binding_check warning: imx8mm-tqma8mqml-mba8mx.dt.yaml: ethernet@30be0000: 'nvmem-cell-names', 'nvmem-cells' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220720063924.1412799-1-alexander.stein@ew.tq-group.comSigned-off-by:
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- 25 Jul, 2022 12 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.gitKalle Valo authored
ath.git patches for v5.20. One fix and rest minor cleanup.
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git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queueDavid S. Miller authored
Tony Nguyen says: ==================== 40GbE Intel Wired LAN Driver Updates 2022-07-22 This series contains updates to i40e and iavf drivers. Przemyslaw adds a helper function for determining whether TC MQPRIO is enabled for i40e. Avinash utilizes the driver's bookkeeping of filters to check for duplicate filter before sending the request to the PF for iavf. ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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Lorenzo Bianconi authored
A typical flow offload scenario for OpenWrt users is routed traffic received by the wan interface that is redirected to a wlan device belonging to the lan bridge. Current implementation fails to fill wdma offload info in mtk_flow_get_wdma_info() since odev device is the local bridge. Fix the issue running dev_fill_forward_path routine in mtk_flow_get_wdma_info in order to identify the wlan device. Tested-by:
Paolo Valerio <pvalerio@redhat.com> Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by:
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David S. Miller authored
Ido Schimmel says: ==================== mlxsw: Spectrum-2 PTP preparations This patchset includes various preparations required for Spectrum-2 PTP support. Most of the changes are non-functional (e.g., renaming, adding registers). The only intentional user visible change is in patch #10 where the PHC time is initialized to zero in accordance with the recommendation of the PTP maintainer. ==================== Signed-off-by: -
Amit Cohen authored
The function mlxsw_sp_ptp_phc_adjfreq() configures MTUTC register to adjust hardware frequency by a given value. This configuration will be same for Spectrum-2. In preparation for Spectrum-2 PTP support, rename the function to not be Spectrum-1 specific. Later, it will be used for Spectrum-2 also. Signed-off-by:
Amit Cohen <amcohen@nvidia.com> Reviewed-by:
Petr Machata <petrm@nvidia.com> Signed-off-by:
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Amit Cohen authored
Spectrum-1 and Spectrum-2 differ in their time stamping capabilities. The former can be configured to time stamp only a subset of received PTP events (e.g., only Sync), whereas the latter will time stamp all PTP events or none. In preparation for Spectrum-2 PTP support, rename the function that parses the hardware time stamping configuration upon %SIOCSHWTSTAMP to be Spectrum-1 specific. Signed-off-by:
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Amit Cohen authored
Currently, there is one shared structure that holds the required structures for PTP clock. Most of the existing fields are relevant only for Spectrum-1 (cycles, timecounter, and more). Rename the structure to be specific for Spectrum-1 and align the existing code. Add a common structure which includes the structures which will be used also for Spectrum-2. This structure will be returned from clock_init() operation, as the definition is shared between all ASICs' operations. Signed-off-by:
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Amit Cohen authored
Currently, there is one shared structure that holds the required structures and details for PTP. Most of the existing fields are relevant only for Spectrum-1 (hash table, lock for hash table, delayed work, and more). Rename the structure to be specific for Spectrum-1 and align the existing code. Add a common structure which includes 'struct mlxsw_sp *mlxsw_sp' and will be returned from ptp_init() operation, as the definition is shared between all ASICs' operations. Signed-off-by:
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Amit Cohen authored
Currently, the reading of FRC values (high and low) is done using macro which calls to a function. In addition, to calculate the offset of FRC, a simple macro is used. This code can be simplified by adding an helper function and calculating the offset explicitly instead of using an additional macro for that. Add the helper function and convert the existing code. This helper will be used later to read UTC clock. Signed-off-by:
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Amit Cohen authored
As lately recommended in the mailing list[1], set the clock to zero time as part of initialization. The idea is that when the clock reads 'Jan 1, 1970', then it is clearly wrong and user will not mistakenly think that the clock is set correctly. If as part of initialization, the driver sets the clock, user might see correct date and time (maybe with a small shift) and assume that there is no need to sync the clock. Fix the existing code of Spectrum-1 to set the 'timecounter' to zero. [1]: https://lore.kernel.org/netdev/20220201191041.GB7009@hoboy.vegasvil.org/Signed-off-by:
Richard Cochran <richardcochran@gmail.com> Signed-off-by:
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Danielle Ratson authored
Rename the 'read_frc_capable' bit to 'read_clock_capable' since now it can be both the FRC and UTC clocks. Signed-off-by:
Danielle Ratson <danieller@nvidia.com> Reviewed-by:
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Amit Cohen authored
Add a resource identifier for maximum number of FIDs so that it could be later used to query the information from firmware. In Spectrum-2 and Spectrum-3, the correction field of PTP packets which are sent as control packets is not updated at egress port. To overcome this limitation, some packets will be sent as data packets. The header should include FID, which is supposed to be 'Max FID + port - 1'. As preparation, add the required resource, to be able to query the value from firmware later. Signed-off-by:
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